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User Guide

© 2025 Microchip Technology Inc. and its subsidiaries

DS50004041A - 1

Introducon (Ask a Queson)

The FPGA-in-the-Loop (FIL)-HSP-IP core is designed to be used for MATLAB

®

design development and

verication on real hardware using the MathWorks FIL simulation methodology on Microchip PolarFire

®

Evaluation kit (MPF300-EVAL-KIT-TS).

Summary

The following table provides a summary of the FIL-HSP-IP core characteristics.

Table 1. FIL-HSP-IP Core Summary

Core VersionThis document applies to FIL-HSP-IP_PF Core v3.0.100.

Supported Device FamiliesPolarFire

®

Supported Tool FlowLibero

®

Included with IP CoreFree

Key Features

This section lists the following key features of the FIL-HSP-IP core.

•Provides connectivity between MathWorks Simulink and PolarFire

®

Evaluation kit over Ethernet.

•Supports Ethernet speed of 1 Gbps

InstallaonInstrucons

MPF300TS_EVAL_KIT v3.0.100 must be installed to the Libero SoC IP Catalog, either automatically through the IP

Catalog update function or manually from the catalog. Once installed, the IP core can be congured, generated

and instantiated within SmartDesign to include in the Libero project.

FIL-HSP-IP Core User Guide

Produktspecifikationer