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 2007-2015 Microchip Technology Inc. DS70000195G-page 1

HIGHLIGHTS

This section of the manual contains the following major topics:

1.0 Introduction ....................................................................................................................... 2

2.0 I

C Bus Characteristics..................................................................................................... 4

3.0 Control and Status Registers ............................................................................................ 8

4.0 Enabling I

C Operation ................................................................................................... 18

5.0 Communicating as a Master in a Single Master Environment ........................................ 20

6.0 Communicating as a Master in a Multi-Master Environment .......................................... 34

7.0 Communicating as a Slave ............................................................................................. 37

8.0 Connection Considerations for I

C Bus .......................................................................... 61

9.0 Operation in Power-Saving Modes ................................................................................. 63

10.0 Peripheral Module Disable (PMDx) Registers ................................................................ 63

11.0 Effects of a Reset............................................................................................................ 63

12.0 Constant-Current Source ................................................................................................ 64

13.0 Register Maps................................................................................................................. 66

14.0 Design Tips ..................................................................................................................... 67

15.0 Related Application Notes............................................................................................... 68

16.0 Revision History .............................................................................................................. 69

Inter-Integrated Circuit (I2C)

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Inter-Integrated Circuit (I

Figure 1-1: I

C Block Diagram

I2CxRCV

Internal

Data Bus

SCLx

SDAx

Shift

Match Detect

Clock

Address Match

Clock

Stretching

I2CxTRN

LSB

Shift Clock

BRG

Reload

Control

or T

(1)

Acknowledge

Generation

I2CxCONH

I2CxSTAT

Control Logic

Read

LSB

Write

Read

I2CxBRG

I2CxRSR

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Down Counter

I2CxCONL

Write

Read

Note 1: Refer to the specific device data sheet for the clock rate.

I2CxADD

Start and Stop

Bit Detect

Start and Stop

Bit Generation

Collision

Detect

I2CxMSK

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2.0 I2C BUS CHARACTERISTICS

The I

C bus is a 2-wire serial interface. Figure 2-1 illustrates the schematic of an I

C connection

between a dsPIC33/PIC24 device and a 24LC256 I

C serial EEPROM, which is a typical

example for any I

C interface.

The I

C interface uses a comprehensive protocol to ensure reliable transmission and reception

of the data. When communicating, one device acts as the “master” and it initiates transfer on the

bus, and generates the clock signals to permit that transfer, while the other devices act as the

“slave” responding to the transfer. The clock line, SCLx, is output from the master and input to

the slave, although occasionally the slave drives the SCLx line. The data line, SDAx, may be

output and input from both the master and slave.

Because the SDAx and SCLx lines are bidirectional, the output stages of the devices driving the

SDAx and SCLx lines must have an open-drain in order to perform the wired-AND function of the bus.

External pull-up resistors are used to ensure a high level when no device is pulling the line down.

In the I

C interface protocol, each device has an address. When a master needs to initiate a data

transfer, it first transmits the address of the device that it wants to “communicate”. All of the

devices “listen” to see if this is their address. Within this address, bit 0 specifies whether the

master wants to read from or write to the slave device. The master and slave are always in

opposite modes (Transmitter or Receiver) of operation during a data transfer. That is, they

operate in either of the following two relationships:

• Master-Transmitter and Slave-Receiver

• Slave-Transmitter and Master-Receiver

In both cases, the master originates the SCLx clock signal.

Figure 2-1: Typical I

C Interconnection Block Diagram

Note:

SCLx and SDAx must be configured as digital.

SCLx

SDAx

dsPIC33/PIC24

SDA

SCL

2.2 k24LC256

(typical)

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2.2 Message Protocol

A typical I

C message is illustrated in Figure 2-3. In this example, the message will read a

specified byte from a 24LC256 I

C serial EEPROM. The dsPIC33/PIC24 device will act as the

master and the 24LC256 device will act as the slave.

Figure 2-3 illustrates the data as driven by the master device and the slave device, taking into

account that the combined SDAx line is a wired-AND of the master and slave data. The master

device controls and sequences the protocol. The slave device will only drive the bus at

specifically determined times.

Figure 2-3: A Typical I

C Message: Read of Serial EEPROM (Random Address Mode)

2.2.1 START MESSAGE

Each message is initiated with a Start condition and terminated with a Stop condition. The

number of data bytes transferred between the Start and Stop conditions is determined by the

master device. As defined by the system protocol, the bytes of the message may have special

meaning, such as the device address byte or the data byte.

2.2.2 ADDRESS SLAVE

In Figure 2-3, the first byte is the device address byte, which must be the first part of any I

message. It contains a device address and a R/W status bit. Note that R/W = 0 for this first

address byte, indicating that the master will be a transmitter and the slave will be a receiver.

2.2.3 SLAVE ACKNOWLEDGE

The receiving device is obliged to generate an Acknowledge signal, ACK, after the reception of

each byte. The master device must generate an extra SCLx clock, which is associated with this

Acknowledge bit.

2.2.4 MASTER TRANSMIT

The next two bytes, sent by the master to the slave, are data bytes that contain the location of

the requested EEPROM data byte. The slave must Acknowledge each of the data bytes.

2.2.5 REPEATED START

The slave EEPROM has the required address information that is required to return the requested

data byte to the master. However, the R/W status bit from the first device address byte specifies

the master transmission and the slave reception. The direction of the bus must be reversed for

the slave to send data to the master.

To perform this function without ending the message, the master sends a Repeated Start. The

Repeated Start is followed with a device address byte containing the same device address as

before, and with R/W = 1, to indicate the slave transmission and the master reception.

Bus

Master

SDAx

Start

Address

Byte

EEPROM Address

High Byte

EEPROM Address

Low Byte Address

Byte Data

Byte

S1 0 1 0 AAA0

210 R1 0 1 0 AAA1

210 P

Slave

SDAx

Activity

AAAA

Output

Idle

R/W

ACK

Restart

ACK

NACK

Stop

Idle

R/W

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Inter-Integrated Circuit (I

R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0

I2CEN — I2CSIDL SCLREL IPMIEN

( )1

A10M DISSLW SMEN

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

Legend:

HC = Hardware Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15

I2CEN:

I2Cx Enable bit

1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0 = Disables the I2Cx module; all the I

C pins are controlled by port functions

bit 14

Unimplemented:

Read as ‘0’

bit 13

I2CSIDL:

I2Cx Stop in Idle Mode bit

1 = Discontinues the module operation when a device enters the Idle mode

0 = Continues the module operation in the Idle mode

bit 12

SCLREL:

SCLx Release Control bit (when operating as I

C slave)

1 = Releases the SCLx clock

0 = Holds the SCLx clock low (clock stretch)

If STREN = 1:

User software may write ‘0’ to initiate a clock stretch and write ‘1’ to release the clock. Hardware clears

at the beginning of every slave data byte transmission. Hardware clears at the end of every slave

address byte reception. Hardware clears at the end of every slave data byte reception.

If STREN = 0:

User software may only write ‘1’ to release the clock. Hardware clears at the beginning of every slave

data byte transmission. Hardware clears at the end of every slave address byte reception.

bit 11

IPMIEN:

IPMI Enable bit

( )1

1 = IPMI Support mode is enabled, all addresses are Acknowledged

0 = IPMI Support mode is disabled

bit 10

A10M:

10-Bit Slave Address bit

1 = I2CxADD register is a 10-bit slave address

0 = I2CxADD register is a 7-bit slave address

bit 9

DISSLW:

Disable Slew Rate Control bit

1 = Slew rate control is disabled

0 = Slew rate control is enabled

bit 8

SMEN:

SMBus Input Levels bit

1 = Enables the I/O pin thresholds compliant with the SMBus specification

0 = Disables the SMBus input thresholds

bit 7

GCEN:

General Call Enable bit (when operating as I

C slave)

1 = Enables the interrupt when a general call address is received in the I2CxRSR register (module is

enabled for reception)

0 = Disables the general call address

bit 6

STREN:

SCLx Clock Stretch Enable bit (I

C Slave mode only; used in conjunction with the SCLREL bit)

1 = Enables the user software or the receive clock stretching

0 = Disables the user software or the receive clock stretching

Note 1:

The IPMIEN bit should not be set when the I

C module is operating as a master.

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Inter-Integrated Circuit (I

R/W-0 U-0 R/W-0, HC R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

I2CEN — I2CSIDL SCLREL

( )1

STRICT A10M DISSLW SMEN

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

Legend:

HC = Hardware Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15

I2CEN:

I2Cx Enable bit

1 = Enables the I

C module and configures the SDAx and SCLx pins as serial port pins

0 = Disables the I

C module; all the I

C pins are controlled by port functions

bit 14

Unimplemented:

Read as ‘0’

bit 13

I2CSIDL:

I2Cx Stop in Idle Mode bit

1 = Discontinues the module operation when a device enters Idle mode

0 = Continues the module operation in the Idle mode

bit 12

SCLREL:

SCLx Release Control bit (I

C Slave mode only)

( )1

Module resets and (I2CEN = 0) sets SCLREL = 1.

If STREN = 0:

( )2

1 = Releases the clock

0 = Forces clock low (clock stretch)

If STREN = 1:

1 = Releases the clock

0 = Holds clock low (clock stretch); the user may program this bit to ‘0’, clock stretch at next SCLx low

bit 11

STRICT:

Strict I

C Reserved Address Rule Enable bit

1 = Strict reserved addressing is enforced; for reserved addresses

In a Slave mode, the device does not respond to reserved address space and the addresses falling

in that category are NACKed.

In a Master mode, the device is allowed to generate addresses with the reserved address space.

0 = Reserved addressing would be Acknowledged

In a Slave mode, the device will respond to an address falling in the reserved address space. When

there is a match with any of the reserved addresses, the device will generate an ACK.

In a Master mode, it is reserved.

bit 10

A10M:

10-Bit Slave Address Flag bit

1 = I2CxADD is a 10-bit slave address

0 = I2CxADD is a 7-bit slave address

bit 9

DISSLW:

Slew Rate Control Disable bit

1 = Slew rate control is disabled for Standard Speed mode (100 kHz, disabled for 1 MHz mode)

0 = Slew rate control is enabled for High-Speed mode (400 kHz)

bit 8

SMEN:

SMBus Input Levels Enable bit

1 = Enables the input logic; therefore, thresholds are compliant with the SMBus specification

0 = Disables the SMBus protocol-specific inputs

Note 1:

Automatically cleared to ‘0’ at the beginning of the slave transmission; automatically cleared to ‘0’ at the

end of the slave reception.

Automatically cleared to ‘0’ at the beginning of the slave transmission.

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bit 7

GCEN:

General Call Enable bit (I

C Slave mode only)

1 = Enables the interrupt when a general call address is received in I2CxRSR; the module is enabled for

reception

0 = General call address is disabled

bit 6

STREN:

SCLx Clock Stretch Enable bit

In I

C Slave mode only; used in conjunction with the SCLREL bit.

1 = Enables clock stretching

0 = Disables clock stretching

bit 5

ACKDT:

Acknowledge Data bit

In I

C Master mode during Master Receive mode. The value that will be transmitted when the user

initiates an Acknowledge sequence at the end of a receive.

In I

C Slave mode when AHEN = 1 or DHEN = 1. The value that the slave will transmit when it initiates

an Acknowledge sequence at the end of an address or data reception.

1 = NACK is sent

0 = ACK is sent

bit 4

ACKEN:

Acknowledge Sequence Enable bit

In I

C Master mode only; applicable during Master Receive mode.

1 = Initiates the Acknowledge sequence on the SDAx and SCLx pins, and transmits the ACKDT data bit

0 = Acknowledge sequence is in Idle mode

bit 3

RCEN:

Receive Enable bit (I

C Master mode only)

1 = Enables Receive mode for I

C; automatically cleared by hardware at the end of an 8-bit receive

data byte

0 = Receive sequence is not in progress

bit 2

PEN:

Stop Condition Enable bit (I

C Master mode only)

1 = Initiates the Stop condition on the SDAx and SCLx pins

0 = Stop condition is in Idle mode

bit 1

RSEN:

Restart Condition Enable bit (I

C Master mode only)

1 = Initiates the Restart condition on the SDAx and SCLx pins

0 = Restart condition is in Idle mode

bit 0

SEN:

Start Condition Enable bit (I

C Master mode only)

1 = Initiates the Start condition on the SDAx and SCLx pins

0 = Start condition is in Idle mode

Note 1:

Automatically cleared to ‘0’ at the beginning of the slave transmission; automatically cleared to ‘0’ at the

end of the slave reception.

Automatically cleared to ‘0’ at the beginning of the slave transmission.

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Inter-Integrated Circuit (I

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

Unimplemented:

Read as ‘0’

bit 6

PCIE:

Stop Condition Interrupt Enable bit (I

C Slave mode only)

1 = Enables the interrupt on detection of a Stop condition

0 = Stop detection interrupts are disabled

bit 5

SCIE:

Start Condition Interrupt Enable bit (I

C Slave mode only)

1 = Enables the interrupt on detection of a Start or Restart condition

0 = Start detection interrupts are disabled

bit 4

BOEN:

Buffer Overwrite Enable bit (I

C Slave mode only)

1 = The I2CxRCV register is updated and an ACK is generated for a received address or data byte,

ignoring the state of the I2COV bit only if the RBF bit = 0

0 = The I2CxRCV register is only updated when the I2COV bit is clear

bit 3

SDAHT:

SDAx Hold Time Selection bit

( )1

1 = Minimum of 300 ns hold time on SDAx after the falling edge of the SCLx clock

0 = Minimum of 100 ns hold time on SDAx after the falling edge the of SCLx clock

bit 2

SBCDE:

Slave Mode Bus Collision Detect Enable bit (I

C Slave mode only)

If, on the rising edge of the SCLx, SDAx is sampled low when the module is outputting a high state, the

BCL bit is set and the bus goes into Idle mode. This Detection mode is valid only during the data and

ACK transmit sequences.

1 = Enables the slave bus collision interrupts

0 = Disables the slave bus collision interrupts

bit 1

AHEN:

Address Hold Enable bit (I

C Slave mode only)

1 = Following the falling edge of the eighth SCLx clock for a matching received address byte; the

SCLREL bit (I2CxCONL<12>) will be cleared and the SCLx will be held low

0 = Address holding is disabled

bit 0

DHEN:

Data Hold Enable bit (I

C Slave mode only)

1 = Following the eighth falling edge of the SCLx clock for a received data byte; slave hardware clears

the SCLREL bit (I2CxCONL<12>) and SCLx is held low

0 = Data holding is disabled

Note 1:

This bit must be set to ‘0’ for 1 MHz operation.

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5.2 Sending Data to a Slave Device

The transmission of a data byte, a 7-bit device address byte or the second byte of a 10-bit

address is accomplished by writing the appropriate value to the I2CxTRN register. Loading this

1. The user software loads the I2CxTRN register with the data byte to transmit.

2. Writing to the I2CxTRN register sets the TBF bit (I2CxSTAT<0>).

3. The data byte is shifted out through the SDAx pin until all 8 bits are transmitted. Each bit

of address or data will be shifted out onto the SDAx pin after the falling edge of SCLx.

4. On the ninth SCLx clock, the module shifts in the ACK bit from the slave device and writes

its value into the ACKSTAT status bit (I2CxSTAT<15>).

5. The module generates the MI2CxIF interrupt at the end of the ninth SCLx clock cycle.

The module does not generate or validate the data bytes. The contents and usage of the bytes

are dependent on the state of the message protocol maintained by the user software.

The sequence of events that occur during master transmission and master reception are

provided in Figure 5-3.

Figure 5-3: Master Transmission Timing Diagram

D7 D6 D5 D4 D3 D2 D1 D0

SCLx (Master)

SCLx (Slave)

SDAx (Master)

SDAx (Slave)

TBF

I2CxTRN

MI2CxIF Interrupt

BRG

5 6 7 81 2 3 4

Writing to the I2CxTRN register will start a master transmission event. The TBF status bit is set.1

The BRG starts. The Most Significant Byte (MSB) of the I2CxTRN register drives SDAx. SCLx remains low. 2

The BRG times out. SCLx is released and the BRG restarts.3

The BRG times out. SCLx is driven low. After SCLx is detected low, the next bit of the I2CxTRN register drives SDAx.4

While SCLx is low, the slave can also pull SCLx low to initiate a Wait (clock stretch).5

Master has already released SCLx and slave can release to end the Wait. The BRG restarts.6

At the falling edge of the eighth SCLx clock, the master releases SDAx. The TBF status bit is cleared.

At the falling edge of the ninth SCLx clock, the master generates the interrupt. SCLx remains low until the next event.8

The slave releases SDAx and the TRSTAT status bit is clear.

C Bus State (Q) (D) (Q) (A) (Q)(D) (Q)

TRSTAT

ACKSTAT

The TRSTAT status bit is set.

The slave drives an ACK/NACK.

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Inter-Integrated Circuit (I

5.2.1 SENDING A 7-BIT ADDRESS TO THE SLAVE

Sending a 7-bit device address involves sending one byte to the slave. A 7-bit address byte must

contain the 7 bits of the I

C device address and a R/W status bit that defines whether the

message will be a write to the slave (master transmission and slave reception) or a read from the

slave (slave transmission and master reception).

5.2.2 STRICT SUPPORT IN MASTER MODE

The master device is allowed to generate an address that falls in the reserved address space if the

STRICT bit (I2CxCONL<11>) is set. For more information on the reserved address, refer to Table 7-2.

5.2.3 SENDING A 10-BIT ADDRESS TO THE SLAVE

Sending a 10-bit device address involves sending two bytes to the slave. The first byte contains 5 bits

of the I

C device address reserved for 10-Bit Addressing modes and 2 bits of the 10-bit address. As

the next byte, which contains the remaining 8 bits of the 10-bit address, must be received by the slave,

the R/W status bit in the first byte must be ‘0’, indicating master transmission and slave reception. If

the message data is also directed toward the slave, the master can continue sending data. However,

if the master expects a reply from the slave, a Repeated Start sequence with the R/W status bit at ‘1’

will change the R/W state of the message to a read of the slave.

5.2.4 RECEIVING ACKNOWLEDGE FROM THE SLAVE

On the falling edge of the eighth SCLx clock, the TBF status bit is cleared and the master will

deassert the SDAx pin, allowing the slave to respond with an Acknowledge. The master will then

generate a ninth SCLx clock.

This allows the slave device being addressed to respond with an ACK bit during the ninth bit time

if an address match occurs or data was received properly. A slave sends an Acknowledge when

it has recognized its device address (including a general call) or when the slave has properly

received its data.

The status of ACK is written into the ACKSTAT bit (I2CxSTAT<15>) on the falling edge of the

ninth SCLx clock. After the ninth SCLx clock, the module generates the MI2CxIF interrupt and

enters into the Idle state until the next data byte is loaded into the I2CxTRN register.

5.2.5 ACKSTAT STATUS FLAG

The ACKSTAT bit (I2CxSTAT<15>) is cleared when the slave has sent an Acknowledge

(ACK = 0) and is set when the slave does not Acknowledge (ACK = 1).

5.2.6 TBF STATUS FLAG

When transmitting, the TBF status bit (I2CxSTAT<0>) is set when the CPU writes to the I2CxTRN

5.2.7 IWCOL STATUS FLAG

If the user software attempts to write to the I2CxTRN register when a transmit is already in

progress (that is, the module is still shifting a data byte), the IWCOL status bit (I2CxSTAT<7>) is

set and the contents of the buffer are unchanged (the write does not occur). The IWCOL status

bit must be cleared in the user software.

Note:

In a 7-Bit Addressing mode, each node using the I

C protocol should be configured

with a unique address that is stored in the I2CxADD register.

While transmitting the address byte, the master must shift the address bits<7:0>,

left by 1 bit, and configure bit 0 as the R/W bit.

Note:

In a 10-Bit Addressing mode, each node using the I

C protocol should be configured

with a unique address that is stored in the I2CxADD register.

While transmitting the first address byte, the master must shift the address

bits<9:8>, left by one bit, and configure bit 0 as the R/W bit.

Note:

Because queuing of events is not allowed, writing to the lower 5 bits of the I2CxCON

or I2CxCONL register is disabled until the transmit condition is complete.

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5.6 Generating a Repeated Start Bus Event

Setting the RSEN bit (I2CxCON<1> or I2CxCONL<1>) enables the generation of a master

Repeated Start sequence, as illustrated in Figure 5-8.

To generate a Repeated Start condition, the user software sets the RSEN bit. The master module

asserts the SCLx pin low. When the module samples the SCLx pin low, the module releases the

SDAx pin for 1 T

BRG

. When the BRG times out and the module samples SDAx high, the module

deasserts the SCLx pin. When the module samples the SCLx pin high, the BRG reloads and

begins counting. SDAx and SCLx must be sampled high for 1 T

BRG

. This action is then followed

by assertion of the SDAx pin low for 1 T

BRG

while SCLx is high.

The following is the Repeated Start sequence:

1. The slave detects the Start condition, sets the S status bit (I2CxSTAT<3>) and clears the

P status bit (I2CxSTAT<4>).

2. The RSEN bit is automatically cleared.

3. The I

C module generates the MI2CxIF interrupt.

5.6.1 IWCOL STATUS FLAG

If the user software writes the I2CxTRN register when a Repeated Start sequence is in progress,

the IWCOL status bit (I2CxSTAT<7>) is set and the contents of the buffer are not changed (the

write does not occur).

Figure 5-8: Master Repeated Start Timing Diagram

Note:

The lower 5 bits of the I2CxCON or I2CxCONL register must be ‘0’ (master logic

inactive) before attempting to set the RSEN bit.

Note:

Because queuing of events is not allowed, writing of the lower 5 bits of the I2CxCON

or I2CxCONL register is disabled until the Repeated Start condition is complete.

SCLx (Master)

SDAx (Master)

RSEN

MI2CxIF Interrupt

BRG

1 2 3 5

Writing RSEN = 1 initiates a master Repeated Start event.

BRG

BRG starts. Module drives SCLx low and

The BRG times out. Module releases SCLx. 2

BRG restarts.

The BRG times out. Module drives SDAx low.3

Slave logic detects Start. Module sets S = 1 and P = 0.4

C Bus State (Q)

BRG

(Q)

BRG restarts.

The BRG times out. Module drives SCLx low.5

Module clears RSEN. Master generates the interrupt.

(Q)

releases SDAx.

(S)

DS70000195G-page 30  2007-2015 Microchip Technology Inc.

Figure 5-9: Master Message (Typical I

C Message: Read of Serial EEPROM)

1 Setting the SEN bit begins a Start event.

AKDT

ACKEN

SEN

SCLx

SDAx

SCLx

SDAx

I2CxTRN

TBF

I2CxRCV

RBF

MI2CxIF

ACKSTAT

1 2 3 4 5 6 7 8

A1 A0

PEN

RCEN

1 2 3 4 5 6 7 8

A11

A10

1 2 3 4 5 6 7 8 9

1 1

RSEN

1 2 3 4 5 6 7 8 9

1 32

1 2 3 4 5 6 7

D3 D2 DD7 D6 D5 D4AA

4 5 7

2Writing the I2CxTRN register starts a master transmission. The data is the serial

3 Writing the I2CxTRN register starts a master transmission. The data is the first

Writing the I2CxTRN register starts a master transmission6

Setting the RCEN bit starts a master reception. On interrupt,

Setting the ACKEN bit starts an Acknowledge event. ACK

Setting the PEN bit starts a master Stop event.

EEPROM device address byte, with the R/W status bit clear, indicating a write.

byte of the EEPROM data address.

the serial EEPROM device address byte, but with R/W statu

the I2CxRCV register, which clears the RBF status bit.

0 0 A2 A7 A6 A5 A4 A2 A1 A0 A1 A0 R

1 10 0 A2

0 0 0 0

Writing the I2CxTRN register starts a master transmission. The data is the second

byte of the EEPROM data address.

Setting the RSEN bit starts a Repeated Start event.

(Master)

(Slave)

MI2CxIF Interrupt Flag Cleared by User Software

 2007-2015 Microchip Technology Inc. DS70000195G-page 31

Figure 5-10: Master Message (7-Bit Address: Transmission and Reception)

1Setting the SEN bit begins a Start event.

AKDT

ACKEN

SEN

SCLx

SDAx

SCLx

SDAx

I2CxTRN

TBF

I2CxRCV

RBF

MI2CxIF

ACKSTAT

1 2 3 4 5 6 7 8

A2 A1

PEN

RCEN

1 2 3 4 5 6 7 8

D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9

RSEN

1 32

9 1 2 3 4 5 6 7

D3 D2 DD7 D6 D5 D4A

4 5 6 7

2 Writing the I2CxTRN register starts a master transmission. The data is the

3 Writing the I2CxTRN register starts a master transmission. The data is the

4 Setting the PEN bit starts a master Stop event.

5Setting the SEN bit begins a Start event. An interrupt is generated on completion

6Writing the I2CxTRN register starts a master transmis

7Setting the RCEN bit starts a master reception.

8Setting the ACKEN bit starts an Acknowledge event. AC

Setting the PEN bit starts a master Stop event.

address byte with the R/W status bit clear.

message byte.

A7 A6 A5 A4 A3

A2 A1 RA7 A6 A5 A4 A3

address byte with the R/W status bit set.

(Master)

(Slave)

MI2CxIF Interrupt Flag Cleared by User Software

of the Start event.

dsPIC33/PIC24 Family Reference Manual

DS70000195G-page 36  2007-2015 Microchip Technology Inc.

6.6 Bus Collision During a Repeated Start Condition

When the two masters do not collide throughout an address byte, a bus collision can occur when

one master attempts to assert a Repeated Start while another transmits data. In this case, the

master generating the Repeated Start loses arbitration and generates a bus collision interrupt.

6.7 Bus Collision During Message Bit Transmission

The most typical case of data collision occurs while the master is attempting to transmit the

device address byte, a data byte or an Acknowledge bit.

If the user software is properly checking the bus state, it is unlikely that a bus collision will occur

on a Start condition. However, because another master can, at the same time, check the bus and

initiate its own Start condition, it is likely that SDAx arbitration will occur and synchronize the Start

of two masters. In this condition, both masters begin and continue to transmit their messages

until one master loses arbitration on a message bit. The SCLx clock synchronization keeps the

two masters synchronized until one loses arbitration. Figure 6-2 illustrates an example of the

message bit arbitration.

Figure 6-2: Bus Collision During Message Bit Transmission

6.8 Bus Collision During a Stop Condition

If the master software loses track of the state of the I

C bus, many existing conditions can

cause a bus collision during a Stop condition. In this case, the master generating the Stop

condition will lose arbitration and generate a bus collision interrupt.

Note:

The bus collision interrupt is not available on all devices. Refer to the specific device

data sheet for availability.

SCLx (Master)

SDAx (Master)

TBF

BRG

1 2 3

Master transmits bit value of ‘1’ in the next SCLx clock.1

BRG

Module releases SDAx.

Another master on bus transmits the bit value of ‘0’

in the next SCLx clock. Another master pulls SDAx low.

BRG times out. Module attempts to verify SDAx high.3

C Bus State

BCL

(D)

SCLx (Bus)

SDAx (Bus)

Bus collision detected.

Module releases SDAx and SCLx. Module sets BCL status bit

and clears the TBF status bit. Master generates the interrupt.

(D)(Q)

(Q) (Q)

MI2CxIF Interrupt

dsPIC33/PIC24 Family Reference Manual

DS70000195G-page 38  2007-2015 Microchip Technology Inc.

7.3 Detecting the Address

Once the module has been enabled, the slave waits for a Start condition to occur. After a Start,

depending on the A10M bit (I2CxCON<10> or I2CxCONL<10>), the slave attempts to detect a

7-bit or 10-bit address. The slave compares one received byte for a 7-bit address or two received

bytes for a 10-bit address. A 7-bit address also contains an R/W status bit that specifies the direc-

tion of the data transfer after the address. If R/W = 0, a write is specified and the slave receives

data from the master. If R/W = 1, a read is specified and the slave sends data to the master. The

10-bit address contains an R/W status bit; however, by definition, it is always R/W = 0 because

the slave must receive the second byte of the 10-bit address.

7.3.1 SLAVE ADDRESS MASKING

The I2CxMSK register masks the address bit positions, designating them as “don’t care” bits for

both 10-Bit and 7-Bit Addressing modes. When a bit in the I2CxMSK register is set (= 1), the

slave responds when the bit in the corresponding location of the address is a ‘0’ or ‘1’. For

example, in 7-Bit Slave mode with I2CxMSK = 0100000, the slave module Acknowledges

addresses, ‘0000000’ and ’0100000’, as valid.

To enable address masking, the IPMI must be disabled by clearing the IPMIEN bit (I2CxCON<11>).

7.3.2 7-BIT ADDRESS AND SLAVE WRITE

After the Start condition, the module shifts 8 bits into the I2CxRSR register, as illustrated in

Figure 7-2. The value of the I2CxRSR register is evaluated against that of the I2CxADD and

I2CxMSK registers on the falling edge of the eighth clock (SCLx). If the address is valid (that is,

an exact match between unmasked bit positions), the following events occur:

• An ACK is generated if the AHEN bit is clear

• The D/A and R/W status bits are cleared

• The module generates the SI2CxIF interrupt on the falling edge of the ninth SCLx clock

• The module waits for the master to send data

Figure 7-2: Slave Write 7-Bit Address Detection Timing Diagram

Note:

The AHEN bit may not be available on all devices. Refer to the specific device data

sheet for availability. If this bit is not present, then the device will generate an (ACK)

on an address match.

SCLx (Master)

SDAx (Master)

SDAx (Slave)

SI2CxIF Interrupt

4 5

Detecting Start bit enables1

C Bus State

(D) (D) (A)(D)

A5A6A7 A4 A3 A2 A1

D/A

ADD10

SCLREL

R/W

address detection. If SCIE is set, then

R/W = 0 indicates that slave 3

receives data bytes.

Valid address of first byte clears D/A

status bit. Slave generates an ACK.

R/W status bit cleared. Slave

generates interrupt.

Bus waiting. Slave ready to6

receive data.

R/W = 0

(S) (Q)

2User software clears the interrupt

flag.

(1)

Note 1: The SCIE bit may not be available on all devices. Refer to the specific device data sheet for availability.

the slave interrupt is asserted.

(1)

 2007-2015 Microchip Technology Inc. DS70000195G-page 39

Inter-Integrated Circuit (I

7.3.3 7-BIT ADDRESS AND SLAVE WRITE WITH THE AHEN AND DHEN BITS

The slave device reception, with the AHEN and DHEN bits set, operates with extra interrupts and

clock stretching added after the eighth falling edge of SCLx. These additional interrupts allow the

slave software to decide whether it wants to ACK the receive address or data byte, rather than

the hardware. This functionality adds support for the PMBus™ that was not present on previous

versions of this module.

Note:

The SI2CxIF interrupt is still set after the ninth falling edge of the SCLx clock, even

if there is no clock stretching and the RBF bit has been cleared. The SI2CxIF

interrupt is not asserted if a NACK is sent to the master.

Produktspecifikationer

Varumärke:	Microchip
Kategori:	Inte kategoriserad
Modell:	PIC24FJ64GA106

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