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© 2009-2012 Microchip Technology Inc. DS61154C-page 34-1
Controller Area
Network (CAN)
34
Section 34. Controller Area Network (CAN)
HIGHLIGHT
This section of the manual contains the following topics:
34.1 Introduction..............................................................................................................34-2
34.2 CAN Message Formats ...........................................................................................34-4
34.3 CAN Registers.........................................................................................................34-9
34.4 Enabling and Disabling the CAN Module ..............................................................34-47
34.5 CAN Module Operating Modes.............................................................................. 34-47
34.6 CAN Message Handling ....................................................................................... 34-49
34.7 Transmitting a CAN Message................................................................................ 34-56
34.8 CAN Message Filtering.......................................................................................... 34-68
34.9 Receiving a CAN Message....................................................................................34-75
34.10 Bit Timing...............................................................................................................34-83
34.11 CAN Error Management ........................................................................................ 34-87
34.12 CAN Interrupts.......................................................................................................34-90
34.13 CAN Received Message Time Stamping............................................................... 34-94
34.14 Power-Saving Modes ............................................................................................34-95
34.15 Related Application Notes .....................................................................................34-96
34.16 Revision History..................................................................................................... 34-97
PIC32 Family Reference Manual
DS61154C-page 34-2 © 2009-2012 Microchip Technology Inc.
34.1 INTRODUCTION
The PIC32 Controller Area Network (CAN) module implements the CAN Specification 2.0B,
which is used primarily in industrial and automotive applications. This asynchronous serial data
communication protocol provides reliable communication in an electrically noisy environment.
The PIC32 device family integrates up to two CAN modules. Figure 34-1 illustrates a typical CAN
bus topology.
Figure 34-1: Typical CAN Bus Network
The CAN module supports the following key features:
Standards Compliance:
- Full CAN Specification 2.0B compliance
- Programmable bit rate up to 1 Mbps
Message Reception and Transmission:
- 32 message FIFOs
- Each FIFO can have up to 32 messages for a total of 1024 messages
- FIFO can be a transmit message FIFO or a receive message FIFO
- User-defined priority levels for message FIFOs used for transmission
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for message filtering
- Automatic response to Remote Transmit Request (RTR)
- DeviceNet™ addressing support
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “Controller Area Network (CAN)
chapter in the current device data sheet to check whether this document supports
the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
CAN
bus
CAN1
PIC®
with Integrated
ECAN
CAN
Transceiver
dsPIC33F
with Integrated
ECAN™
dsPIC30F
with Integrated
CAN
Transceiver
CAN Transceiver
CAN
Transceiver
CAN
CAN2
CAN
Transceiver
PIC32
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-3
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
Additional Features:
- Loopback, Listen All Messages and Listen-Only modes for self-test, system diagnostics
and bus monitoring
- Low-power operating modes
- CAN module is a bus master on the PIC32 system bus
- Does not require Direct Memory Access (DMA) channels for operation
- Dedicated time stamp timer
- Data-only Message Reception mode
Figure 34-2 illustrates the general structure of the CAN module.
Figure 34-2: PIC32 CAN Module Block Diagram
The CAN module consists of a protocol engine, message acceptance filters and Message
Assembly Buffers (MABs). The protocol engine transmits and receives messages to and from the
CAN bus (as per CAN Specification 2.0B). Received messages are assembled in the receive
message assembly buffer. The received message is then filtered by the message acceptance
filters. The transmit message assembly buffer holds the message to be transmitted as it is
processed by the protocol engine.
The CAN message buffers reside in device RAM. There are no CAN message buffers in the CAN
module. Therefore, all messages are stored in device RAM. The CAN module is a bus master on
the PIC32 system bus, and will read and write data to device RAM as required. The CAN module
does not use DMA for its operation and fetches messages from the device RAM without DMA or
CPU intervention.
Message Buffer 31
Message Buffer 1
Message Buffer 0
Message Buffer 31
Message Buffer 1
Message Buffer 0
Message Buffer 31
Message Buffer 1
Message Buffer 0
FIFO0 FIFO1 FIFO31
Device RAM
Up to 32 Message Buffers
CAN Message FIFO (up to 32 FIFOs)
Message
Buffer Size
2 or 4 Words
System Bus
CPU
CAN Module
32 Filters
4 Masks
CxTX
CxRX
PIC32 Family Reference Manual
DS61154C-page 34-4 © 2009-2012 Microchip Technology Inc.
34.2 CAN MESSAGE FORMATS
The CAN bus protocol uses asynchronous communication. Information is passed from the
transmitters to receivers in data frames, which are composed of byte fields that define the
contents of the data frame as illustrated in Figure 34-3.
Each frame begins with a Start of Frame (SOF) bit field and terminates with an End of Frame
(EOF) bit field. The SOF is followed by the Arbitration and Control fields, which identify the
message type, format, length and priority. This information allows each node on the CAN bus to
respond appropriately to the message. The Data field conveys the message content and is of
variable length, ranging from 0 bytes to 8 bytes. Error protection is provided by the Cyclic
Redundancy Check (CRC) and Acknowledgement (ACK) fields.
Figure 34-3: CAN Bus Message Frame
The CAN bus protocol supports four frame types:
Data Frame – carries data from transmitter to the receivers
Remote Frametransmitted by a node on the bus, to request transmission of a data
frame with the same identifier from another node
Error Frametransmitted by any node when it detects an error
Overload Frame provides an extra delay between successive Data or remote frames
Interframe Space provides a separation between successive frames
The CAN Specification 2.0B defines two additional data formats:
Standard Data Frame intended for standard messages that use 11 identifier bits
Extended Data Frame – intended for extended messages that use 29 identifier bits
There are three CAN Specification versions:
2.0Aconsiders 29-bit identifier as error
2.0B Passive – ignores 29-bit identifier messages
2.0B Active – handles both 11-bit and 29-bit identifiers
The PIC32 CAN module is compliant with the CAN Specification 2.0B, while providing enhanced
message filtering capabilities.
Note: For detailed information on the CAN protocol, refer to the Bosch CAN Bus
Specification 2.0B, which is available for download at:
http://www.semiconductors.bosch.de
S
O
F
E
O
F
ARBITRATION CONTROL DATA ACKCRC
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-5
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
34.2.1 Standard Data Frame
The standard data frame message begins with an SOF bit followed by a 12-bit Arbitration field
as illustrated in Figure 34-4. The Arbitration field contains an 11-bit identifier and RTR bit. The
identifier defines the type of information contained in the message, and is used by each receiving
node to determine if the message is of interest to it. The RTR bit distinguishes a data frame from
a remote frame. For a standard data frame, the RTR bit is clear.
Following the Arbitration field is a 6-bit Control field, which provides more information about the
contents of the message. The first bit in the Control field is an Identifier Extension (IDE) bit, which
distinguishes the message as either a standard or extended data frame. A standard data frame
is indicated by a dominant state (logic level 0’) during transmission of the IDE bit. The second
bit in the Control field is a reserved (RB0) bit, which is in the dominant state (logic level 0’). The
last four bits in the Control field represent the Data Length Code (DLC), which specifies the
number of data bytes present in the message.
The Data field follows the Control field. This field carries the message data – the actual payload
of the data frame. This field is of variable length, ranging from 0 bytes to eight bytes. The number
of bytes is user-selectable.
The Data field is followed by the CRC field, which is a 15-bit CRC sequence with one delimiter bit.
The Acknowledgement (ACK) field is sent as a recessive bit (logic level 1’), and is overwritten
as a dominant bit by any receiver that has received the data correctly. The message is
acknowledged by the receiver regardless of the result of the acceptance filter comparison.
The last field is the EOF field, which consists of seven recessive bits that indicate the end of
message.
Figure 34-4: Format of the Standard Data Frame
SID10 SID1
S
O
F
IDENTIFIER
11 Bits
R
T
R
I
D
E
RB0 DLC
4 Bits
DATA
8 Bytes
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID0
9/19/2006 - 9/26/2006
11-bit Identifier
Interframe Space
9/19/2006 - 9/26/2006 9/19/2006 - 9/26/2006
Data
9/19/2006 - 9/26/2006
9/19/2006 - 9/26/2006
9 - 9/26/2006
Frame Interframe Space
9/19/2006 - 9/26/2006
IDE is Dominant (Logical ‘0’)
RTR is Dominant (Logical ‘0’)
RB0 is Dominant (Logical ‘0’)
/19/
Arbitration
Field
Control
Field
Field
CRC
Field
ACK
Field
End-of-
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-7
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
34.2.3 Remote Frame
A node expecting to receive data from another node can initiate transmission of the respective
data by the source node, by sending a remote frame. A remote frame can be in standard format
(Figure Figure 34-6) or the extended format ( 34-7).
A Remote frame is similar to a data frame, with the following exceptions:
The RTR bit is recessive (RTR = 1)
There is no Data field (DLC = 0)
Figure 34-6: Format of the Standard Remote Frame
Figure 34-7: Format of the Extended Remote Frame
SID10 SID1
S
O
F
IDENTIFIER
11 Bits
R
T
R
I
D
E
DLC
4 Bits
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID0
11-bit Identifier
RB0
IDE is Dominant (Logical ‘0’)
RTR is Recessive (Logical ‘1’)
RB0 is Dominant (Logical ‘0’)
Arbitration Field Control Field CRC Field ACK Field End of Frame
SID10 SID0
S
O
F
IDENTIFIER
11 Bits
S
R
R
I
D
E
R
T
R
DLC
4 Bits
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID1
Arbitration Field
29-bit Identifier
Control Field CRC Field
IDENTIFIER
18 Bits
EID17 EID1 EID0
R
B
1
R
B
0
IDE is Recessive (Logical ‘1’)
SRR is Recessive (Logical 1’)
RTR is Recessive (Logical ‘1’)
RB0 is Dominant (Logical ‘0’)
RB1 is Dominant (Logical ‘0’)
ACK Field
End of
Frame
PIC32 Family Reference Manual
DS61154C-page 34-8 © 2009-2012 Microchip Technology Inc.
34.2.4 Error Frame
An error frame is generated by any node that detects a bus error. An error frame consists of an
Error Flag field followed by an Error Delimiter field. The Error Delimiter consists of eight recessive
bits and allows the bus nodes to restart communication cleanly after an error has occurred. There
are two types of error flag fields, depending on the error status of the node that detects the error:
Error Active Flag – contains six consecutive dominant bits, which forces all other nodes
on the network to generate Error Echo Fags, thereby resulting in a series of 6 to 12
dominant bits on the bus
Error Passive Flag contains six consecutive recessive bits, with the result that unless
the bus error is detected by the transmitting node, the transmission of an Error Passive
Flag will not affect the communication of any other node on the network
34.2.5 Overload Frame
An Overload Frame can be generated by a node either when a dominant bit is detected during
Interframe Space or when a node is not ready to receive the next message (for example, if it is
still reading the previous received message). An Overload Frame has the same format as an
Error Frame with an Active Error Flag, but can only be generated during Interframe Space. It
consists of an Overload Fag field with six dominant bits followed by an Overload Delimiter field
with eight recessive bits. A node can generate a maximum of two sequential overload frames to
delay the start of the next message.
34.2.6 Interframe Space
Interframe Space separates successive frames being transmitted on the CAN bus. It consists of
at least three recessive bits, referred to as intermission. The Interframe Space allows nodes time
to internally process the previously received message before the start of the next frame. If the
transmitting node is in the Error Passive state, an additional eight recessive bits will be inserted
in the Interframe Space before any other message is transmitted by the node. This period is
called a Suspend Transmit field and allows time for other transmitting nodes to take control of the
bus.
PIC32 Family Reference Manual
DS61154C-page 34-10 © 2009-2012 Microchip Technology Inc.
34.3.4 CAN Module Control Registers
CiFIFOBA: CAN Message Buffer Base Address Register
This register holds the base (start) address of the CAN message buffer area. This is a
physical address.
CiFIFOCONn: CAN FIFO Control Register (n = 0 through 31)
These registers allow the control and configuration of CAN Message FIFOs.
CiFIFOINTn: CAN FIFO Interrupt Register (n = 0 through 31)
These registers allow the individual FIFO interrupt sources to be enabled or disabled. They
also contain interrupt status bits.
CiFIFOUAn: CAN FIFO User Address Register (n = 0 through 31)
These registers provide the addr the CAN message FIFO from ess of the memory location in
where the next message can be read or where the next message should be written to.
CiFIFOCIn: CAN Module Message Index Register (n = 0 through 31)
These registers provide the message buffer index (in the message FIFO) of the next
message that the CAN module will transmit or where the next received message will be
saved.
Table 34-1 provides a summary of all CAN-related registers. Corresponding registers appear
after the summary, followed by a detailed description of each register. All unimplemented
registers and/or bits within a register read as zeros.
PIC32 Family Reference Manual
DS61154C-page 34-14 © 2009-2012 Microchip Technology Inc.
Register 34-1: CiCON: CAN Module Control Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24 U-0 U-0U-0 U-0 S/HC-0 R/W-1 R/W-0 R/W-0
— ABAT REQOP<2:0>
23:16 R-1 R-0 R-0 R/W-0 U-0 U-0 U-0 U-0
OPMOD<2:0> CANCAP —
15:8 R/W-0 U-0 U-0R/W-0 U-0 R-0 U-0 U-0
ON(1) — —SIDLE CANBUSY
7:0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DNCNT<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 Unimplemented: Read as 0
bit 27 ABAT: Abort All Pending Transmissions bit
1 = Signal all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions aborted
bit 26-24 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved; do not use
101 = Reserved; do not use
100 = Set Configuration mode
011 = Set Listen-Only mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 23-21 OPMOD<2:0>: Operation Mode Status bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen-Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit
1 = CANTMR value is stored on valid message reception and is stored with the message
0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power
bit 19-16 Unimplemented: Read as 0
bit 15 ON: CAN On bit(1)
1 = CAN module is enabled
0 = CAN module is disabled
bit 14 Unimplemented: Read as 0
Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-15
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
bit 13 SIDLE: CAN Stop in Idle bit
1 = CAN Stops operation when system enters Idle mode
0 = CAN continues operation when system enters Idle mode
bit 12 Unimplemented: Read as 0
bit 11 CANBUSY: CAN Module is Busy bit
1 = The CAN module is active
0 = The CAN module is completely disabled
bit 10-5 Unimplemented: Read as 0
bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits
11111 = Invalid Selection (compare up to 18-bits of data with EID)
10011 = Invalid Selection (compare up to 18-bits of data with EID)
10010 = Compare up to data byte 2 bit 6 with EID17 (CiRXFn<17>)
00001 = Compare up to data byte 0 bit 7 with EID0 (CiRXFn<0>)
00000 = Do not compare data bytes
Register 34-1: CiCON: CAN Module Control Register (Continued)
Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.
PIC32 Family Reference Manual
DS61154C-page 34-16 © 2009-2012 Microchip Technology Inc.
Register 34-2: CiCFG: CAN Baud Rate Configuration Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0U-0
— —
23:16 U-0 R/W-0 R/W-0 R/W-0U-0 U-0 U-0 R/W-0
— — WAKFIL SEG2PH<2:0>(1,4)
15:8 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0
SEG2PHTS(1) SAM(2) SEG1PH<2:0> PRSEG<2:0>
7:0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0
SJW<1:0>(3) BRP<5:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0
bit 22 WAKFIL: CAN Bus Line Filter Enable bit
1 = Use CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 21-19 Unimplemented: Read as ‘0
bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits
(1,5)
111 = Length is 8 x TQ
000 = Length is 1 x TQ
bit 15 SEG2PHTS: Phase Segment 2 Time Select bit
(1)
1 = Freely programmable
0 = Maximum of SEG1PH or Information Processing Time, whichever is greater
bit 14 SAM: Sample of the CAN Bus Line bit(2)
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits
(4)
111 = Length is 8 x TQ
000 = Length is 1 x TQ
Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).
PIC32 Family Reference Manual
DS61154C-page 34-20 © 2009-2012 Microchip Technology Inc.
Register 34-4: CiVEC: CAN Interrupt Code Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — FILHIT<4:0>
7:0 U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— ICODE<6:0>(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0
bit 12-8 Filter Hit Number bitFILHIT<4:0>:
11111 = Filter 31
11110 = Filter 30
00001 = Filter 1
00000 = Filter 0
bit 7 Unimplemented: Read as ‘0
bit 6-0 ICODE<6:0>: Interrupt Flag Code bits(1)
1111111 = Reserved
1001000 = Reserved
1001000 = Invalid message received (IVRIF)
1000111 = CAN module mode change (MODIF)
1000110 = CAN timestamp timer (CTMRIF)
1000101 = Bus bandwidth error (SERRIF)
1000100 = Address error interrupt (SERRIF)
1000011 = Receive FIFO overflow interrupt (RBOVIF)
1000010 = Wake-up interrupt (WAKIF)
1000001 = Error Interrupt (CERRIF)
1000000 = No interrupt
0111111 = Reserved
0100000 = Reserved
0011111 = FIFO31 Interrupt (CiFSTAT<31> set)
0011110 = FIFO30 Interrupt (CiFSTAT<30> set)
0000001 = FIFO1 Interrupt (CiFSTAT<1> set)
0000000 = FIFO0 Interrupt (CiFSTAT<0> set)
Note 1: These bits are only updated for enabled interrupts.
PIC32 Family Reference Manual
DS61154C-page 34-24 © 2009-2012 Microchip Technology Inc.
Register 34-10: CiFLTCON0: CAN Filter Control Register 0
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0
FLTEN3 MSEL3<1:0> FSEL3<4:0>
23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0
FLTEN2 MSEL2<1:0> FSEL2<4:0>
15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0
FLTEN1 MSEL1<1:0> FSEL1<4:0>
7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0
FLTEN0 MSEL0<1:0> FSEL0<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set x = Bit is unknown‘0’ = Bit is cleared
bit 31 FLTEN3: Filter 3 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL3<1:0>: Filter 3 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL3<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN2: Filter 2 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL2<1:0>: Filter 2 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL2<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-25
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
bit 15 FLTEN1: Filter 1 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL1<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN0: Filter 0 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL0<1:0>: Filter 0 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL0<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Register 34-10: CiFLTCON0: CAN Filter Control Register 0 (Continued)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
PIC32 Family Reference Manual
DS61154C-page 34-26 © 2009-2012 Microchip Technology Inc.
Register 34-11: CiFLTCON1: CAN Filter Control Register 1
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0
FLTEN7 MSEL7<1:0> FSEL7<4:0>
23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0
FLTEN6 MSEL6<1:0> FSEL6<4:0>
15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0
FLTEN5 MSEL5<1:0> FSEL5<4:0>
7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0
FLTEN4 MSEL4<1:0> FSEL4<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN7: Filter 7 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL7<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN6: Filter 6 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL6<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-27
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
bit 15 FLTEN5: Filter 5 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL5<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN4: Filter 4 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL4<1:0>: Filter 4 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL4<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Register 34-11: CiFLTCON1: CAN Filter Control Register 1 (Continued)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-29
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
bit 15 FLTEN9: Filter 9 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL9<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN8: Filter 8 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL8<1:0>: Filter 8 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL8<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Register 34-12: CiFLTCON2: CAN Filter Control Register 2 (Continued)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-39
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
bit 15 FLTEN29: Filter 29 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL29<1:0>: Filter 29 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL29<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN28: Filter 28 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL28<1:0>: Filter 28 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL28<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Register 34-17: CiFLTCON7: CAN Filter Control Register 7 (Continued)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
PIC32 Family Reference Manual
DS61154C-page 34-40 © 2009-2012 Microchip Technology Inc.
Register 34-18: CiRXFn: CAN Acceptance Filter n Register 7 (n = 0 through 31)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-xR/W-x R/W-x
SID<10:3>
23:16 R/W-x R/W-x R/W-x R/W-0 R/W-x R/W-xU-0 U-0
SID<2:0> — EXID EID<17:16>
15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-xR/W-x R/W-x
EID<15:8>
7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-xR/W-x R/W-x
EID<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 SID<10:0>: Standard Identifier bits
1 1 = Message address bit SIDx must be ‘ ’ to match filter
0 0 = Message address bit SIDx must be ‘ ’ to match filter
bit 20 Unimplemented: Read as ‘0
bit 19 EXID: Extended Identifier Enable bits
1 = Match only messages with extended identifier addresses
0 = Match only messages with standard identifier addresses
bit 18 Unimplemented: Read as ‘0
bit 17-0 EID<17:0>: Extended Identifier bits
1 1 = Message address bit EIDx must be ‘ ’ to match filter
0 0 = Message address bit EIDx must be ‘ ’ to match filter
Note: This register can only be modified when the filter is disabled (FLTENn = 0).
PIC32 Family Reference Manual
DS61154C-page 34-42 © 2009-2012 Microchip Technology Inc.
Register 34-20: CiFIFOCONn: CAN FIFO Control Register (n = 0 through 31)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0U-0
— — — — — — — —
23:16 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — FSIZE<4:0>(1)
15:8 U-0 U-0 U-0 U-0S/HC-0 S/HC-0 R/W-0 U-0
FRESET UINC DONLY(1) — — — —
7:0 R/W-0 R/W-0 R/W-0R-0 R-0 R-0 R/W-0 R/W-0
TXEN TXABAT(2) TXLARB(3) TXERR(3) TXREQ RTREN TXPR<1:0>
Legend: S = Settable bit HC = Hardware clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0
bit 20-16 FSIZE<4:0>: FIFO Size bits(1)
11111 = FIFO is 32 messages deep
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep
bit 15 Unimplemented: Read as ‘0
bit 14 FRESET: FIFO Reset bits
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should
poll if this bit is clear before taking any action
0 = No effect
bit 13 UINC: Increment Head/Tail bit
TXEN = 1: (FIFO configured as a Transmit FIFO)
When this bit is set the FIFO head will increment by a single message
TXEN = 0: (FIFO configured as a Receive FIFO)
When this bit is set the FIFO tail will increment by a single message
bit 12 DONLY: Store Message Data Only bit(1)
TXEN = 1: (FIFO configured as a Transmit FIFO)
This bit is not used and has no effect.
TXEN = 0: (FIFO configured as a Receive FIFO)
1 = Only data bytes will be stored in the FIFO
0 = Full message is stored, including identifier
bit 11-8 Unimplemented: Read as 0
bit 7 TXEN: TX/RX Buffer Selection bit
1 = FIFO is a Transmit FIFO
0 = FIFO is a Receive FIFO
Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the FIFO is reset.
PIC32 Family Reference Manual
DS61154C-page 34-44 © 2009-2012 Microchip Technology Inc.
Register 34-21: CiFIFOINTn: CAN FIFO Interrupt Register (n = 0 through 31)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24 U-0 U-0 U-0 U-0U-0 R/W-0 R/W-0 R/W-0
— — — — TXNFULLIE TXHALFIE TXEMPTYIE
23:16 U-0 U-0 U-0U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE
15:8 U-0 U-0 U-0 U-0 R-0 R-0 R-0U-0
— — — — TXNFULLIF(1) TXHALFIF TXEMPTYIF(1)
7:0 U-0 U-0 U-0 R-0 R-0 R-0U-0 R/W-0
— — — — RXOVFLIF RXFULLIF(1) RXHALFIF(1) RXNEMPTYIF(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as 0
bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full
0 = Interrupt disabled for FIFO not full
bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty
0 = Interrupt disabled for FIFO empty
bit 23-20 Unimplemented: Read as 0
bit 19 RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event
0 = Interrupt disabled for overflow event
bit 18 RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full
0 = Interrupt disabled for FIFO full
bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 16 RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty
0 = Interrupt disabled for FIFO not empty
bit 15-11 Unimplemented: Read as 0
bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is not full
0 = FIFO is full
TXEN = 0: (FIFO configured as a Receive Buffer)
Unused, reads ‘0
Note 1: This bit is read-only and reflects the status of the FIFO.

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Modell: PIC32MX564F064L

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