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Controller Area

Network (CAN)

Section 34. Controller Area Network (CAN)

HIGHLIGHT

This section of the manual contains the following topics:

34.1 Introduction..............................................................................................................34-2

34.2 CAN Message Formats ...........................................................................................34-4

34.3 CAN Registers.........................................................................................................34-9

34.4 Enabling and Disabling the CAN Module ..............................................................34-47

34.5 CAN Module Operating Modes.............................................................................. 34-47

34.6 CAN Message Handling ....................................................................................... 34-49

34.7 Transmitting a CAN Message................................................................................ 34-56

34.8 CAN Message Filtering.......................................................................................... 34-68

34.9 Receiving a CAN Message....................................................................................34-75

34.10 Bit Timing...............................................................................................................34-83

34.11 CAN Error Management ........................................................................................ 34-87

34.12 CAN Interrupts.......................................................................................................34-90

34.13 CAN Received Message Time Stamping............................................................... 34-94

34.14 Power-Saving Modes ............................................................................................34-95

34.15 Related Application Notes .....................................................................................34-96

34.16 Revision History..................................................................................................... 34-97

PIC32 Family Reference Manual

34.1 INTRODUCTION

The PIC32 Controller Area Network (CAN) module implements the CAN Specification 2.0B,

which is used primarily in industrial and automotive applications. This asynchronous serial data

communication protocol provides reliable communication in an electrically noisy environment.

The PIC32 device family integrates up to two CAN modules. Figure 34-1 illustrates a typical CAN

bus topology.

Figure 34-1: Typical CAN Bus Network

The CAN module supports the following key features:

• Standards Compliance:

- Full CAN Specification 2.0B compliance

- Programmable bit rate up to 1 Mbps

• Message Reception and Transmission:

- 32 message FIFOs

- Each FIFO can have up to 32 messages for a total of 1024 messages

- FIFO can be a transmit message FIFO or a receive message FIFO

- User-defined priority levels for message FIFOs used for transmission

- 32 acceptance filters for message filtering

- Four acceptance filter mask registers for message filtering

- Automatic response to Remote Transmit Request (RTR)

- DeviceNet™ addressing support

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “Controller Area Network (CAN)”

chapter in the current device data sheet to check whether this document supports

the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

CAN

bus

CAN1

PIC®

with Integrated

ECAN

CAN

Transceiver

dsPIC33F

with Integrated

ECAN™

dsPIC30F

with Integrated

CAN

Transceiver

CAN Transceiver

CAN

Transceiver

CAN

CAN2

CAN

Transceiver

PIC32

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

• Additional Features:

- Loopback, Listen All Messages and Listen-Only modes for self-test, system diagnostics

and bus monitoring

- Low-power operating modes

- CAN module is a bus master on the PIC32 system bus

- Does not require Direct Memory Access (DMA) channels for operation

- Dedicated time stamp timer

- Data-only Message Reception mode

Figure 34-2 illustrates the general structure of the CAN module.

Figure 34-2: PIC32 CAN Module Block Diagram

The CAN module consists of a protocol engine, message acceptance filters and Message

Assembly Buffers (MABs). The protocol engine transmits and receives messages to and from the

CAN bus (as per CAN Specification 2.0B). Received messages are assembled in the receive

message assembly buffer. The received message is then filtered by the message acceptance

filters. The transmit message assembly buffer holds the message to be transmitted as it is

processed by the protocol engine.

The CAN message buffers reside in device RAM. There are no CAN message buffers in the CAN

module. Therefore, all messages are stored in device RAM. The CAN module is a bus master on

the PIC32 system bus, and will read and write data to device RAM as required. The CAN module

does not use DMA for its operation and fetches messages from the device RAM without DMA or

CPU intervention.

Message Buffer 31

Message Buffer 1

Message Buffer 0

Message Buffer 31

Message Buffer 1

Message Buffer 0

Message Buffer 31

Message Buffer 1

Message Buffer 0

FIFO0 FIFO1 FIFO31

Device RAM

Up to 32 Message Buffers

CAN Message FIFO (up to 32 FIFOs)

Message

Buffer Size

2 or 4 Words

System Bus

CPU

CAN Module

32 Filters

4 Masks

CxTX

CxRX

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

34.3 CAN REGISTERS

The CAN module registers can be classified by their function into the following groups:

• Module and CAN bit rate Configuration registers

• Interrupt and Status registers

• Mask and Filter Configuration registers

• FIFO Control registers

34.3.1 Module and CAN Bit Rate Configuration Registers

•CiCON: CAN Module Control Register

This register is used to set up the CAN module operational mode and DeviceNet

addressing.

•CiCFG: CAN Baud Rate Configuration Register

This register contains control bits to set the period of each time quantum, using the baud rate

prescaler, and specifies Synchronization Jump Width (SJW) in terms of time quanta. It is

also used to program the number of time quanta in each CAN bit segment, including the

propagation and phase segments 1 and 2.

34.3.2 Interrupt and Status Registers

•CiINT: CAN Interrupt Register

This register allows various CAN module interrupt sources to be enabled and disabled. It

also contains interrupt status flags.

•CiVEC: CAN Interrupt Code Register

This register provides status bits which provide information on CAN module interrupt source

and message filter hits. These values can be used to implement a jump table for handling

different cases.

•CiTREC: CAN Transmit/Receive Error Count Register

This register provides information on Transmit and Receive Error Counter values. It also has

bits which indicate various warning states.

•CiFSTAT: CAN FIFO Status Register

This register contains interrupt status flag for all the FIFOs.

•CiRXOVF: CAN Receive FIFO Overflow Status Register

This register contains overflow interrupt status flag for all the FIFOs.

•CiTMR: CAN TImer Register

This register contains CAN Message Timestamp timer and a Prescaler.

34.3.3 Mask and Filter Configuration Registers

•CiRXMn: CAN Acceptance Filter Mask n Register (n = 0, 1, 2 or 3)

These registers allow the configuration of the filter masks. A total of four masks are

available.

•CiFLTCON0: CAN Filter Control Register 0 through CiFLTCON7: CAN Filter Control

These registers allow the association of FIFO and Masks with a filter. A Filter can be

associated with any one mask. It also contains a filter enable/disable bit.

•CiRXFn: CAN Acceptance Filter n Register 7 (n = 0 through 31)

These registers specify the filter to be applied to the received message. A total of 32 filters

are available.

Note: The ‘i’ shown in the register identifier denotes CAN1 or CAN2.

PIC32 Family Reference Manual

CiRXM3(1) 31:24 SID<10:3>

23:16 SID<2:0> MIDE-— — EID<17:16>

15:8 EID<15:8>

7:0 EID<7:0>

CiFLTCON0(1) 31:24 FLTEN3 MSEL3<1:0> FSEL3<4:0>

23:16 FLTEN2 MSEL2<1:0> FSEL2<4:0>

15:8 FLTEN1 MSEL1<1:0> FSEL1<4:0>

7:0 FLTEN0 MSEL0<1:0> FSEL0<4:0>

CiFLTCON1(1) 31:24 FLTEN7 MSEL7<1:0> FSEL7<4:0>

23:16 FLTEN6 MSEL6<1:0> FSEL6<4:0>

15:8 FLTEN5 MSEL5<1:0> FSEL5<4:0>

7:0 FLTEN4 MSEL4<1:0> FSEL4<4:0>

CiFLTCON2(1) 31:24 FLTEN11 MSEL11<1:0> FSEL11<4:0>

23:16 FLTEN10 MSEL10<1:0> FSEL10<4:0>

15:8 FLTEN9 MSEL9<1:0> FSEL9<4:0>

7:0 FLTEN8 MSEL8<1:0> FSEL8<4:0>

CiFLTCON3(1) 31:24 FLTEN15 MSEL15<1:0> FSEL15<4:0>

23:16 FLTEN14 MSEL14<1:0> FSEL14<4:0>

15:8 FLTEN13 MSEL13<1:0> FSEL13<4:0>

7:0 FLTEN12 MSEL12<1:0> FSEL12<4:0>

CiFLTCON4(1) 31:24 FLTEN19 MSEL19<1:0> FSEL19<4:0>

23:16 FLTEN18 MSEL18<1:0> FSEL18<4:0>

15:8 FLTEN17 MSEL17<1:0> FSEL17<4:0>

7:0 FLTEN16 MSEL16<1:0> FSEL16<4:0:

CiFLTCON5(1) 31:24 FLTEN23 MSEL23<1:0> FSEL23<4:0>

23:16 FLTEN22 MSEL22<1:0> FSEL22<4:0>

15:8 FLTEN21 MSEL21<1:0> FSEL21<4:0>

7:0 FLTEN20 MSEL20<1:0> FSEL20<4:0>

CiFLTCON6(1) 31:24 FLTEN27 MSEL27<1:0> FSEL27<4:0>

23:16 FLTEN26 MSEL26<1:0> FSEL26<4:0>

15:8 FLTEN25 MSEL25<1:0> FSEL25<4:0>

7:0 FLTEN24 MSEL24<1:0> FSEL24<4:0>

CiFLTCON7(1) 31:24 FLTEN31 MSEL31<1:0> FSEL31<4:0>

23:16 FLTEN30 MSEL30<1:0> FSEL30<4:0>

15:8 FLTEN29 MSEL29<1:0> FSEL29<4:0>

7:0 FLTEN28 MSEL28<1:0> FSEL28<4:0>

CiRXFn(1)

(n = 0 through 31)

31:24 SID<10:3>

23:16 SID<2:0> -— EXID — EID<17:16>

15:8 EID<15:8>

7:0 EID<7:0>

CiFIFOBA(1) 31:24 CiFIFOBA<31:24>

23:16 CiFIFOBA<23:16>

15:8 CiFIFOBA<15:8>

7:0 CiFIFOBA<7:0>

CiFIFOCONn(1)

(n = 0 through 31)

31:24 — — — — — — — —

23:16 — — — FSIZE<4:0>

15:8 — FRESET UINC DONLY — — — —

7:0 TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPR<1:0>

Table 34-1: CAN Controller Register Summary (Continued)

Name Bit

Range

Bit

31/2315/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

Legend: ‘—’ = unimplemented; read as ‘0’.

Note 1: This register has an associated Clear, Set, and Invert register at an offset of 0x4, 0x8, or 0xC bytes, respectively. These registers have

the same name with CLR, SET, or INV appended to the end of the register name (For example, CiCONCLR). Writing a ‘1’ to any bit

position in these registers will clear, set, or invert valid bits in the associated register. Reads from these registers should be ignored.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 13 CAN Bus Error Interrupt Flag bitCERRIF:

1 = A CAN bus error has occurred

0 = A CAN bus error has not occurred

bit 12 SERRIF: System Error Interrupt Flag bit

1 = A system error occurred (typically an illegal address was presented to the system bus)

0 = A system error has not occurred

bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit

1 = A receive buffer overflow has occurred

0 = A receive buffer overflow has not occurred

bit 10-4 Unimplemented: Read as ‘0’

bit 3 MODIF: CAN Mode Change Interrupt Flag bit

1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP)

0 = A CAN module mode change has not occurred

bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit

1 = A CAN timer (CANTMR) overflow has occurred

0 = A CAN timer (CANTMR) overflow has not occurred

bit 1 RBIF: Receive Buffer Interrupt Flag bit

1 = A receive buffer interrupt is pending

0 = A receive buffer interrupt is not pending

bit 0 TBIF: Transmit Buffer Interrupt Flag bit

1 = A transmit buffer interrupt is pending

0 = A transmit buffer interrupt is not pending

Note 1: This bit can only be cleared by turning the CAN module OFF and ON by clearing or setting the ON bit

(CiCON<15>).

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — FILHIT<4:0>

7:0 U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0

— ICODE<6:0>(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as ‘0’

bit 12-8 Filter Hit Number bitFILHIT<4:0>:

11111 = Filter 31

11110 = Filter 30

•

00001 = Filter 1

00000 = Filter 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 ICODE<6:0>: Interrupt Flag Code bits(1)

1111111 = Reserved

•

1001000 = Reserved

1001000 = Invalid message received (IVRIF)

1000111 = CAN module mode change (MODIF)

1000110 = CAN timestamp timer (CTMRIF)

1000101 = Bus bandwidth error (SERRIF)

1000100 = Address error interrupt (SERRIF)

1000011 = Receive FIFO overflow interrupt (RBOVIF)

1000010 = Wake-up interrupt (WAKIF)

1000001 = Error Interrupt (CERRIF)

1000000 = No interrupt

0111111 = Reserved

•

0100000 = Reserved

0011111 = FIFO31 Interrupt (CiFSTAT<31> set)

0011110 = FIFO30 Interrupt (CiFSTAT<30> set)

•

0000001 = FIFO1 Interrupt (CiFSTAT<1> set)

0000000 = FIFO0 Interrupt (CiFSTAT<0> set)

Note 1: These bits are only updated for enabled interrupts.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN7 MSEL7<1:0> FSEL7<4:0>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN6 MSEL6<1:0> FSEL6<4:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN5 MSEL5<1:0> FSEL5<4:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN4 MSEL4<1:0> FSEL4<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN7: Filter 7 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL7<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN6: Filter 6 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL6<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN23 MSEL23<1:0> FSEL23<4:0>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN22 MSEL22<1:0> FSEL22<4:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN21 MSEL21<1:0> FSEL21<4:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN20 MSEL20<1:0> FSEL20<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set x = Bit is unknown‘0’ = Bit is cleared

bit 31 FLTEN23: Filter 23 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL23<1:0>: Filter 23 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL23<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN22: Filter 22 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL22<1:0>: Filter 22 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL22<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 15 FLTEN21: Filter 21 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL21<1:0>: Filter 21 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL21<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN20: Filter 20 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL20<1:0>: Filter 20 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL20<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN31 MSEL31<1:0> FSEL31<4:0>

23:16 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN30 MSEL30<1:0> FSEL30<4:0>

15:8 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN29 MSEL29<1:0> FSEL29<4:0>

7:0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN28 MSEL28<1:0> FSEL28<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN31: Filter 31 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL31<1:0>: Filter 31 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL31<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN30: Filter 30 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL30<1:0>: Filter 30 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL30<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0U-0

— — — — — — — —

23:16 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — FSIZE<4:0>(1)

15:8 U-0 U-0 U-0 U-0S/HC-0 S/HC-0 R/W-0 U-0

— FRESET UINC DONLY(1) — — — —

7:0 R/W-0 R/W-0 R/W-0R-0 R-0 R-0 R/W-0 R/W-0

TXEN TXABAT(2) TXLARB(3) TXERR(3) TXREQ RTREN TXPR<1:0>

Legend: S = Settable bit HC = Hardware clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 Unimplemented: Read as ‘0’

bit 20-16 FSIZE<4:0>: FIFO Size bits(1)

11111 = FIFO is 32 messages deep

•

00010 = FIFO is 3 messages deep

00001 = FIFO is 2 messages deep

00000 = FIFO is 1 message deep

bit 15 Unimplemented: Read as ‘0’

bit 14 FRESET: FIFO Reset bits

1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should

poll if this bit is clear before taking any action

0 = No effect

bit 13 UINC: Increment Head/Tail bit

TXEN = 1: (FIFO configured as a Transmit FIFO)

When this bit is set the FIFO head will increment by a single message

TXEN = 0: (FIFO configured as a Receive FIFO)

When this bit is set the FIFO tail will increment by a single message

bit 12 DONLY: Store Message Data Only bit(1)

TXEN = 1: (FIFO configured as a Transmit FIFO)

This bit is not used and has no effect.

TXEN = 0: (FIFO configured as a Receive FIFO)

1 = Only data bytes will be stored in the FIFO

0 = Full message is stored, including identifier

bit 11-8 Unimplemented: Read as ‘0’

bit 7 TXEN: TX/RX Buffer Selection bit

1 = FIFO is a Transmit FIFO

0 = FIFO is a Receive FIFO

Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits

(CiCON<23:21>) = 100).

2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.

3: This bit is reset on any read of this register or when the FIFO is reset.

Produktspecifikationer

Varumärke:	Microchip
Kategori:	Inte kategoriserad
Modell:	PIC32MZ2048ECM100

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6 Mars 2025

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4 Mars 2025

Microchip ATSAMA5D43 Bruksanvisning

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Microchip ATSAMC20E18A Bruksanvisning

2 Mars 2025

Microchip TC620 Bruksanvisning

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Inte kategoriserad Manualer

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