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UXN14M9PE
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UXN14M9P
SMD- Rev E00020
Subject Change Without Noticeto
1 of 10
Features
• Wide Operating Range: DC 14 –
GHz
• Contiguous Divide Ratios: 8 to 511
• Large Output Swings: >1 Vpp/side
• Single-Ended and/or Dierential
Drive
• Size: 6mm x 6mm
• Parallel Control Lines
• Low SSB Phase Noise:
▪ 147 dBc @ 10 kHz Oset
Description
The UXN14M9P is a highly programma-
ble integer divider covering all integer
divide ratios between 8 and 511.
The device features single-ended
or dierential inputs and outputs.
Parallel control inputs are CMOS
and LVTTL compatible for ease of
system integration. The UXN14M9P
is packaged in a 40-pin, 6mm x 6mm
leadless plastic surface mount package.
Key Specifications (T = 25˚C):
Vee -3.3 = V, Iee = 185 mA, Zo=50 Ω
Application
The UXN14M9P can used be as a general
purpose, highly congurable, divider in
a variety of high frequency synthesizer
applications. Fast switching combined with
a wide range of divide ratios make the
UXN14M9P an excellent choice for fraction-
al-N and integer-N PLLs. Fractional division
may be achieved by applying a sequence to
the divider control lines, such as a delta-
sigma modulated sequence.
Pad Metallization
The QFN package pad metallization consists
of a 300-800 micro-inch (typical thickness 435
micro-inch or 11.04um) 100% matte Sn plate.
The plating covers a Cu (C194) leadframe.
The packages are manufactured
with a >1hr 150C annealing/heat treating
process, and the matte (non-glossy) plating,
specically to mitigate tin whisker growth.
Parameter
Description
Min
Typ
Max
Fin (GHz)
Input Frequency
DC*
-
14
Pin (dBm)
Input Power
-
0
+10
Pout (dBm)
Output Power
-
+4
-
PDC (W)
DC Power Dissipation
-
1.1
-
θjc (ºC/W)
Junction-Case Thermal Resistance
-
14
-
* frequency limit dependent input edge speedLow on
14 GHz Divide-by-8 to 511
Programmable Integer Divider
UXN14M9P
SMD- Rev E00020
Subject Change Without Noticeto
2 of 10
Frequency Divider Application
Min/Max Single-Ended Input Power, INP*
Input Sensitivity, T=25º Divide- -10, FRS=0C, by
Min/Max Single-Ended Input Power, INP*
Input Sensitivity, -3.3 Divide- -10, FRS=0V, by
Min/Max Single-Ended Input Power, INP*
Input Sensitivity, T=25º Divide- -10, FRS=1C, by
Min/Max Single-Ended Input Power, INP*
Input Sensitivity, -3.3 Divide- -10, FRS=1V, by
Output Power Output Power
UXN14M9P
SMD- Rev E00020
Subject Change Without Noticeto
3 of 10
Functional Block Diagram
Table 1: Pin Description
Port Name
Description
Notes
INP
Divider Input, Positive Terminal
CML signal levels
INN
Divider Input, Negative Terminal
CML signal levels
OUTP
Divider Output, Positive Terminal
CML signal levels
OUTN
Divider Output, Negative Terminal
CML signal levels
P0-P8
Divider Modulus Control (P8=MSB)
CMOS levels, see Equation 1, defaults to logic 0
VCC
RF & DC Ground
The paddle is connected to +VCC inside the package
VEE
-3.3 V @ 340 mA
Negative Supply Voltage
Equation 3:
Divider Modulus = N = P0 · 20 + P1 · 21 + P2 · 22 + ... + P8 · 28 for 8 ≤ N ≤ 511
Table CMOS Levels for control line P0-2: P8
Simplied Control Logic Schematic
Logic Level
Minimum
Typical
Maximum
1 (High)
Vcc-1.25 V
Vcc-0.8V
Vcc-0.8V
0 (Low)
Vee
Vee
Vee+1.25 V
Produktspecifikationer
| Varumärke: | Microchip |
| Kategori: | Inte kategoriserad |
| Modell: | UXN14M9PE |
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