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© 2020 Microchip Technology Inc.DS60001192D-page 50-1

Section 50. CPU for Devices with MIPS32

®

microAptiv™

and M-Class Cores

This section of the manual contains the following topics:

50.1Introduction..................................................................................................................50-2

50.2Architecture Overview..................................................................................................50-4

50.3PIC32 CPU Details......................................................................................................50-8

50.4Special Considerations When Writing to CP0 Registers...........................................50-13

50.5MIPS32 Architecture..................................................................................................50-14

50.6CPU Bus....................................................................................................................50-15

50.7Internal System Busses.............................................................................................50-15

50.8Set/Clear/Invert..........................................................................................................50-16

50.9ALU Status Bits..........................................................................................................50-16

50.10Interrupt and Exception Mechanism..........................................................................50-17

50.11Programming Model...................................................................................................50-17

50.12Floating Point Unit (FPU)...........................................................................................50-24

50.13Coprocessor 0 (CP0) Registers.................................................................................50-42

50.14Coprocessor 1 (CP1) Registers...............................................................................50-121

50.15microMIPS Execution...............................................................................................50-132

50.16MCU ASE Extension................................................................................................50-132

50.17MIPS DSP ASE Extension.......................................................................................50-133

50.18Memory Model (MCU only)......................................................................................50-133

50.19Memory Management (MPU only)...........................................................................50-135

50.20L1 Caches (MPU only).............................................................................................50-141

50.21CPU Instructions......................................................................................................50-145

50.22MIPS DSP ASE Instructions....................................................................................50-151

50.23CPU Initialization......................................................................................................50-153

50.24Effects of a Reset.....................................................................................................50-154

50.25Related Application Notes........................................................................................50-155

50.26Revision History.......................................................................................................50-156

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