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AVR® Instruction Set Manual

Introduction

This manual gives an overview and explanation of every instruction available for 8-bit AVR

® devices. Each instruction

has its own section containing functional description, it’s opcode, and syntax, the end state of the status register, and

cycle times.

The manual also contains an explanation of the different addressing modes used by AVR devices and an appendix

listing all modern AVR devices and what instruction it has available.

Table of Contents

Introduction.....................................................................................................................................................1

1. Instruction Set Nomenclature..................................................................................................................6

2. CPU Registers Located in the I/O Space................................................................................................8

2.1. RAMPX, RAMPY, and RAMPZ.....................................................................................................8

2.2. RAMPD........................................................................................................................................ 8

2.3. EIND.............................................................................................................................................8

3. The Program and Data Addressing Modes.............................................................................................9

3.1. Register Direct, Single Register Rd..............................................................................................9

3.2. Register Direct - Two Registers, Rd and Rr................................................................................. 9

3.3. I/O Direct.................................................................................................................................... 10

3.4. Data Direct................................................................................................................................. 10

3.5. Data Indirect............................................................................................................................... 11

3.6. Data Indirect with Pre-decrement............................................................................................... 11

3.7. Data Indirect with Post-increment.............................................................................................. 12

3.8. Data Indirect with Displacement.................................................................................................12

3.9. Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions............. 13

3.10. Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction................. 13

3.11. Store Program Memory Post-increment.....................................................................................14

3.12. Direct Program Addressing, JMP and CALL.............................................................................. 14

3.13. Indirect Program Addressing, IJMP and ICALL..........................................................................15

3.14. Extended Indirect Program Addressing, EIJMP and EICALL.....................................................15

3.15. Relative Program Addressing, RJMP and RCALL..................................................................... 16

4. Conditional Branch Summary............................................................................................................... 17

5. Instruction Set Summary.......................................................................................................................18

6. Instruction Description...........................................................................................................................24

6.1. ADC – Add with Carry................................................................................................................ 24

6.2. ADD – Add without Carry........................................................................................................... 25

6.3. ADIW – Add Immediate to Word................................................................................................ 26

6.4. AND – Logical AND....................................................................................................................27

6.5. ANDI – Logical AND with Immediate..........................................................................................28

6.6. ASR – Arithmetic Shift Right...................................................................................................... 29

6.7. BCLR – Bit Clear in SREG......................................................................................................... 30

6.8. BLD – Bit Load from the T Bit in SREG to a Bit in Register....................................................... 31

6.9. BRBC – Branch if Bit in SREG is Cleared..................................................................................32

6.10. BRBS – Branch if Bit in SREG is Set......................................................................................... 33

6.11. BRCC – Branch if Carry Cleared................................................................................................34

6.12. BRCS – Branch if Carry Set....................................................................................................... 35

6.13. BREAK – Break..........................................................................................................................36

6.14. BREQ – Branch if Equal.............................................................................................................36

6.15. BRGE – Branch if Greater or Equal (Signed).............................................................................37

6.16. BRHC – Branch if Half Carry Flag is Cleared.............................................................................38

AVR® Instruction Set Manual

6.17. BRHS – Branch if Half Carry Flag is Set....................................................................................39

6.18. BRID – Branch if Global Interrupt is Disabled............................................................................ 40

6.19. BRIE – Branch if Global Interrupt is Enabled............................................................................. 41

6.20. BRLO – Branch if Lower (Unsigned).......................................................................................... 42

6.21. BRLT – Branch if Less Than (Signed)........................................................................................43

6.22. BRMI – Branch if Minus..............................................................................................................44

6.23. BRNE – Branch if Not Equal...................................................................................................... 45

6.24. BRPL – Branch if Plus................................................................................................................46

6.25. BRSH – Branch if Same or Higher (Unsigned).......................................................................... 47

6.26. BRTC – Branch if the T Bit is Cleared........................................................................................48

6.27. BRTS – Branch if the T Bit is Set............................................................................................... 49

6.28. BRVC – Branch if Overflow Cleared.......................................................................................... 50

6.29. BRVS – Branch if Overflow Set..................................................................................................51

6.30. BSET – Bit Set in SREG............................................................................................................ 52

6.31. BST – Bit Store from Bit in Register to T Bit in SREG................................................................53

6.32. CALL – Long Call to a Subroutine..............................................................................................54

6.33. CBI – Clear Bit in I/O Register....................................................................................................55

6.34. CBR – Clear Bits in Register...................................................................................................... 56

6.35. CLC – Clear Carry Flag..............................................................................................................57

6.36. CLH – Clear Half Carry Flag...................................................................................................... 57

6.37. CLI – Clear Global Interrupt Enable Bit...................................................................................... 58

6.38. CLN – Clear Negative Flag........................................................................................................ 59

6.39. CLR – Clear Register................................................................................................................. 60

6.40. CLS – Clear Sign Flag................................................................................................................61

6.41. CLT – Clear T Bit........................................................................................................................62

6.42. CLV – Clear Overflow Flag.........................................................................................................62

6.43. CLZ – Clear Zero Flag................................................................................................................63

6.44. COM – One’s Complement........................................................................................................ 64

6.45. CP – Compare............................................................................................................................65

6.46. CPC – Compare with Carry........................................................................................................66

6.47. CPI – Compare with Immediate................................................................................................. 67

6.48. CPSE – Compare Skip if Equal..................................................................................................68

6.49. DEC – Decrement...................................................................................................................... 69

6.50. DES – Data Encryption Standard...............................................................................................71

6.51. EICALL – Extended Indirect Call to Subroutine......................................................................... 72

6.52. EIJMP – Extended Indirect Jump............................................................................................... 73

6.53. ELPM – Extended Load Program Memory.................................................................................73

6.54. EOR – Exclusive OR.................................................................................................................. 75

6.55. FMUL – Fractional Multiply Unsigned........................................................................................ 76

6.56. FMULS – Fractional Multiply Signed.......................................................................................... 77

6.57. FMULSU – Fractional Multiply Signed with Unsigned................................................................79

6.58. ICALL – Indirect Call to Subroutine............................................................................................80

6.59. IJMP – Indirect Jump..................................................................................................................81

6.60. IN - Load an I/O Location to Register.........................................................................................82

6.61. INC – Increment......................................................................................................................... 83

6.62. JMP – Jump............................................................................................................................... 84

6.63. LAC – Load and Clear................................................................................................................85

6.64. LAS – Load and Set................................................................................................................... 86

AVR® Instruction Set Manual

3.5 Data Indirect

Figure 3-5. Data Indirect Addressing

X, Y OR Z - POINTER

The operand address is the contents of the X-, Y-, or the Z-pointer. In AVR devices without SRAM, Data Indirect

Addressing is called Register Indirect Addressing.

3.6 Data Indirect with Pre-decrement

Figure 3-6. Data Indirect Addressing with Pre-decrement

X, Y OR Z - POINTER

The X,- Y-, or the Z-pointer is decremented before the operation. The operand address is the decremented contents

of the X-, Y-, or the Z-pointer.

AVR® Instruction Set Manual

The Program and Data Addressing Modes

3.7 Data Indirect with Post-increment

Figure 3-7. Data Indirect Addressing with Post-increment

X, Y OR Z - POINTER

The X-, Y-, or the Z-pointer is incremented after the operation. The operand address is the content of the X-, Y-, or

the Z-pointer before incrementing.

3.8 Data Indirect with Displacement

Figure 3-8. Data Indirect with Displacement

Y OR Z - POINTER

OP Rr/Rd

The operand address is the result of the q displacement contained in the instruction word added to the Y- or

Z-pointer. Rd/Rr specify the destination or source register.

AVR® Instruction Set Manual

The Program and Data Addressing Modes

...........continued

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

IN Rd, A In From I/O Location Rd ← I/O(A) None 1 1 1 1

OUT A, Rr Out To I/O Location I/O(A) ← Rr None 1 1 1 1

PUSH Rr Push Register on Stack STACK ← Rr None 2 1 (1) 1 1

POP Rd Pop Register from Stack Rd ← STACK None 2 2 (1) 2 3

XCH Z, Rd Exchange DS(Z) ↔ Rd None N/A 2 N/A N/A

LAS Z, Rd Load and Set DS(Z)

←

Rd v DS(Z)

DS(Z)

None N/A 2 N/A N/A

LAC Z, Rd Load and Clear DS(Z)

←

(0xFF – Rd) DS(Z)∧

DS(Z)

None N/A 2 N/A N/A

LAT Z, Rd Load and Toggle DS(Z)

←

Rd DS(Z)⊕

DS(Z)

None N/A 2 N/A N/A

Table 5-5. Bit and Bit-Test Instructions

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

LSL Rd Logical Shift Left C

Rd(n+1)

Rd(0)

←

Rd(7)

Rd(n), n=6...0

Z,C,N,V,H 1 1 1 1

LSR Rd Logical Shift Right C

Rd(n)

Rd(7)

←

Rd(0)

Rd(n+1), n=0...6

Z,C,N,V 1 1 1 1

ROL Rd Rotate Left Through Carry temp

Rd(n+1)

Rd(0)

←

Rd(7)

Rd(n), n=6...0

temp

Z,C,N,V,H 1 1 1 1

ROR Rd Rotate Right Through Carry temp

Rd(n)

Rd(7)

←

Rd(0)

Rd(n+1), n=0...6

temp

Z,C,N,V 1 1 1 1

ASR Rd Arithmetic Shift Right C

Rd(n)

Rd(7)

←

Rd(0)

Rd(n+1), n=0..6

Rd(7)

Z,C,N,V 1 1 1 1

SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1 1 1 1

SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 2 1 1 1

CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 2 1 1 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 1 1 1

BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 1 1 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1 1 1 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 1 1 1

SEC Set Carry C ← 1 C 1 1 1 1

CLC Clear Carry C ← 0 C 1 1 1 1

SEN Set Negative Flag N ← 1 N 1 1 1 1

AVR® Instruction Set Manual

Instruction Set Summary

...........continued

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

CLN Clear Negative Flag N ← 0 N 1 1 1 1

SEZ Set Zero Flag Z ← 1 Z 1 1 1 1

CLZ Clear Zero Flag Z ← 0 Z 1 1 1 1

SEI Global Interrupt Enable I ← 1 I 1 1 1 1

CLI Global Interrupt Disable I ← 0 I 1 1 1 1

SES Set Sign Bit S ← 1 S 1 1 1 1

CLS Clear Sign Bit S ← 0 S 1 1 1 1

SEV Set Two’s Complement Overflow V ← 1 V 1 1 1 1

CLV Clear Two’s Complement

Overflow

V ← 0 V 1 1 1 1

SET Set T in SREG T ← 1 T 1 1 1 1

CLT Clear T in SREG T ← 0 T 1 1 1 1

SEH Set Half Carry Flag in SREG H ← 1 H 1 1 1 1

CLH Clear Half Carry Flag in SREG H ← 0 H 1 1 1 1

Table 5-6. MCU Control Instructions

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

BREAK Break See the debug interface description None 1 1 1 1

NOP No Operation None 1 1 1 1

SLEEP Sleep See the power management and sleep description None 1 1 1 1

WDR Watchdog Reset See the Watchdog Controller description None 1 1 1 1

Notes:

1. Cycle times for data memory access assume internal RAM access and are not valid for accessing external

RAM.

2. Cycle time for data memory access assumes internal RAM access, and are not valid for access to NVM.

A minimum of one extra cycle must be added when accessing NVM. The additional time varies dependent

on the NVM module implementation. See the NVMCTRL section in the specific devices data sheet for more

information.

3. If the LD instruction is accessing I/O Registers, one cycle can be deducted.

4. Varies with the programming time of the device.

AVR® Instruction Set Manual

Instruction Set Summary

Table 6-1. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.2 ADD – Add without Carry

6.2.1 Description

Adds two registers without the C flag and places the result in the destination register Rd.

Operation:

(i) (i) Rd ← Rd + Rr

Syntax: Operands: Program Counter:

(i) ADD Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0000 11rd dddd rrrr

6.2.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

H Rd3 Rr3 Rr3 R3 R3 Rd3∧ ∨ ∧ ∨ ∧

Set if there was a carry from bit 3; cleared otherwise.

S N V, for signed tests.⊕

V Rd7 Rr7 R7 Rd7 Rr7 R7∧ ∧ ∨ ∧ ∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

C Rd7 Rr7 Rr7 R7 R7 Rd7∧ ∨ ∧ ∨ ∧

Set if there was a carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

AVR® Instruction Set Manual

Instruction Description

Example:

add r1,r2 ; Add r2 to r1 (r1=r1+r2)

add r28,r28 ; Add r28 to itself (r28=r28+r28)

Words 1 (2 bytes)

Table 6-2. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.3 ADIW – Add Immediate to Word

6.3.1 Description

Adds an immediate value (0-63) to a register pair and places the result in the register pair. This instruction operates

on the upper four register pairs and is well suited for operations on the Pointer Registers.

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) R[d+1]:Rd ← R[d+1]:Rd + K

Syntax: Operands: Program Counter:

(i) ADIW Rd,K d {24,26,28,30}, 0 ≤ K ≤ 63 PC ← PC + 1∈

16-bit Opcode:

1001 0110 KKdd KKKK

6.3.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

–––⇔⇔⇔⇔⇔

S N V, for signed tests.⊕

V Rdh7 R15∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N R15

Set if MSB of the result is set; cleared otherwise.

Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧

Set if the result is ; cleared otherwise.0x0000

C R15 Rdh7∧

AVR® Instruction Set Manual

Instruction Description

Set if there was a carry from the MSB of the result; cleared otherwise.

R (Result) equals R[d+1]:Rd after the operation.

Example:

adiw r24,1 ; Add 1 to r25:r24

adiw ZL,63 ; Add 63 to the Z-pointer(r31:r30)

Words 1 (2 bytes)

Table 6-3. Cycles

Name Cycles

AVRe 2

AVRxm 2

AVRxt 2

AVRrc N/A

6.4 AND – Logical AND

6.4.1 Description

Performs the logical AND between the contents of register Rd and register Rr, and places the result in the destination

Operation:

(i) Rd ← Rd Rr∧

Syntax: Operands: Program Counter:

(i) AND Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0010 00rd dddd rrrr

6.4.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 –⇔ ⇔ ⇔

S N V, for signed tests.⊕

V 0

Cleared.

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

AVR® Instruction Set Manual

Instruction Description

Produktspecifikationer

Varumärke:	Microchip
Kategori:	Inte kategoriserad
Modell:	AVR32DD32

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