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HRPWM with Fine Edge
Placement
dsPIC33/PIC24 Family Reference Manual
Introduction
Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on
the device variant, this manual section may not apply to all dsPIC33 devices. Please consult the note at the
beginning of the chapter in the specific device data sheet to check whether this document supports the device you
are using.
Device data sheets and family reference manual sections are available for download from the Microchip Worldwide
Website at: www.microchip.com.
This document describes the features and use of the High-Resolution Pulse-Width Modulated (PWM) with Fine Edge
Placement. This flexible module provides features to support many types of Motor Control (MC) and Power Control
(PC) applications, including:
• AC-to-DC Converters
• DC-to-DC Converters
• AC and DC Motor Control: Brushed DC, BLDC, PMSM, ACIM, SRM, Stepper, etc.
• Inverters
• Battery Chargers
• Digital Lighting
• Power Factor Correction (PFC)
High-Level Features
• Up to Eight Independent PWM Generators, each with Dual Outputs
• Operating modes:
– Independent Edge PWM mode
– Variable Phase PWM mode
– Independent Edge PWM mode, Dual Output
– Center-Aligned PWM mode
– Double Update Center-Aligned PWM mode
– Dual Edge Center-Aligned PWM mode
• Output modes:
– Complementary
– Independent
– Push-Pull
• Dead-Time Generator
• Dead-Time Compensation
• Leading-Edge Blanking (LEB)
• Output Override for Fault Handling
• Flexible Period/Duty Cycle Updating Options
• PWM Control Inputs (PCI) for PWM Pin Overrides and External PWM Synchronization
• Advanced Triggering Options
• Combinatorial Logic Output
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 1
• PWM Event Outputs
HRPWM with Fine Edge Placement
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 2
Table of Contents
Introduction.....................................................................................................................................................1
High-Level Features....................................................................................................................................... 1
1. Registers................................................................................................................................................. 5
2. Register Maps......................................................................................................................................... 6
2.1. Common Functions Register Map................................................................................................7
2.2. PWM Generator Register Map................................................................................................... 21
3. Architecture Overview...........................................................................................................................51
4. Operation.............................................................................................................................................. 54
4.1. PWM Clocking............................................................................................................................54
4.2. PWM Generator (PG) Features..................................................................................................59
4.3. Common Features......................................................................................................................95
4.4. Lock and Write Restrictions......................................................................................................100
5. Application Examples..........................................................................................................................105
5.1. Six-Step Commutation of Three-Phase BLDC Motor...............................................................105
5.2. Three-Phase Sinusoidal Control of PMSM/ACIM Motors.........................................................114
5.3. Simple Complementary PWM Output.......................................................................................117
5.4. Cycle-by-Cycle Current Limit Mode..........................................................................................118
5.5. External Period Reset Mode.................................................................................................... 120
6. Interrupts............................................................................................................................................. 123
7. Operation in Power-Saving Modes..................................................................................................... 124
7.1. Operation in Sleep Mode..........................................................................................................124
7.2. Operation in Idle Mode............................................................................................................. 124
8. Related Application Notes...................................................................................................................125
9. Revision History.................................................................................................................................. 126
9.1. Revision A (August 2017).........................................................................................................126
9.2. Revision B (February 2018)..................................................................................................... 126
9.3. Revision C (February 2019)..................................................................................................... 126
9.4. Revision D (December 2020)................................................................................................... 126
The Microchip Website...............................................................................................................................128
Product Change Notification Service..........................................................................................................128
Customer Support...................................................................................................................................... 128
Microchip Devices Code Protection Feature..............................................................................................128
Legal Notice............................................................................................................................................... 129
Trademarks................................................................................................................................................ 129
Quality Management System..................................................................................................................... 130
HRPWM with Fine Edge Placement
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 3
Worldwide Sales and Service.....................................................................................................................131
HRPWM with Fine Edge Placement
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 4
2.1 Common Functions Register Map
Note: The number of LOGCONy and PWMEVTy registers are device-dependent. Refer to the device data sheet for
availability.
Name Bit Pos. 7 6 5 4 3 2 1 0
PCLKCON 7:0 DIVSEL[1:0] MCLKSEL[1:0]
15:8 HRRDY HRERR LOCK
FSCL 7:0 FSCL[7:0]
15:8 FSCL[15:8]
FSMINPER 7:0 FSMINPER[7:0]
15:8 FSMINPER[15:8]
MPHASE 7:0 MPHASE[7:0]
15:8 MPHASE[15:8]
MDC 7:0 MDC[7:0]
15:8 MDC[15:8]
MPER 7:0 MPER[7:0]
15:8 MPER[15:8]
LFSR 7:0 LFSR[7:0]
15:8 LFSR[14:8]
CMBTRIGL 7:0 CTA8EN CTA7EN CTA6EN CTA5EN CTA4EN CTA3EN CTA2EN CTA1EN
15:8
CMBTRIGH 7:0 CTB8EN CTB7EN CTB6EN CTB5EN CTB4EN CTB3EN CTB2EN CTB1EN
15:8
LOGCONy 7:0 S1yPOL S2yPOL PWMLFy[1:0] PWMLFyD[2:0]
15:8 PWMS1y[3:0] PWMS2y[3:0]
PWMEVTy 7:0 EVTySEL[3:0] EVTyPGS[2:0]
15:8 EVTyOEN EVTyPOL EVTySTRD EVTySYNC
HRPWM with Fine Edge Placement
Register Maps
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 7
2.1.1 PWM Clock Control Register
Name: PCLKCON
Legend: C = Clearable bit
Bit 15 14 13 12 11 10 9 8
HRRDY HRERR LOCK
Access R R/C R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
DIVSEL[1:0] MCLKSEL[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 – HRRDY High-Resolution Ready
Note: This bit is not present on all devices. Refer to the device-specific data sheet for availability.
Value Description
1The high-resolution circuitry is ready
0The high-resolution circuitry is not ready
Bit 14 – HRERR High-Resolution Error(1,2)
Notes:
1. This bit is not present on all devices. Refer to the device-specific data sheet for availability.
2. User software may write a ‘ ’ to this location to request a reset of the High-Resolution block when HRRDY = .0 1
Value Description
1An error has occurred; PWM signals will have limited resolution
0No error has occurred; PWM signals will have full resolution when HRRDY = 1
Bit 8 – LOCK Lock
Note: A device-specific unlock sequence must be performed before this bit can be cleared. Refer to the device data
sheet for the unlock sequence.
Value Description
1Write-protected registers and bits are locked
0Write-protected registers and bits are unlocked
Bits 5:4 – DIVSEL[1:0] PWM Clock Divider Selection
Value Description
11 Divide ratio is 1:16
10 Divide ratio is 1:8
01 Divide ratio is 1:4
00 Divide ratio is 1:2
Bits 1:0 – MCLKSEL[1:0] PWM Master Clock Selection
Clock sources are device-specific. Refer to the device data sheet for selections.
Note: Do not change the MCLKSEL[1:0] bits while ON (PGxCONL[15]) = .1
HRPWM with Fine Edge Placement
Register Maps
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 8
Produktspecifikationer
| Varumärke: | Microchip |
| Kategori: | Inte kategoriserad |
| Modell: | dsPIC33CK128MP202 |
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