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© 2010-2011 Microchip Technology Inc. DS70645C-page 14-1
High-Speed PWM
14
Section 14. High-Speed PWM
HIGHLIGHTS
This section of the manual contains the following major topics:
14.1 Introduction .................................................................................................................. 14-2
14.2 Features....................................................................................................................... 14-2
14.3 Control Registers ......................................................................................................... 14-3
14.4 Architecture Overview................................................................................................ 14-24
14.5 Module Description .................................................................................................... 14-27
14.6 PWM Operating Modes.............................................................................................. 14-33
14.7 PWM Generator......................................................................................................... 14-71
14.8 PWM Trigger.............................................................................................................. 14-87
14.9 PWM Interrupts.......................................................................................................... 14-98
14.10 PWM Fault Pins ......................................................................................................... 14-99
14.11 Special Features ...................................................................................................... 14-105
14.12 PWM Output Pin Control...........................................................................................14-111
14.13 Immediate Update of PWM Duty Cycle ................................................................... 14-113
14.14 Power-Saving Modes............................................................................................... 14-114
14.15 External Control of Individual Time Base(s)............................................................. 14-114
14.16 Application Information ............................................................................................ 14-115
14.17 Register Map............................................................................................................ 14-126
14.18 Related Application Notes........................................................................................ 14-127
14.19 Revision History ....................................................................................................... 14-128
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-2 © 2010-2011 Microchip Technology Inc.
14.1 INTRODUCTION
This section describes the High-Speed Pulse-Width Modulator (PWM) module and its
associated operational modes. The High-Speed PWM module in the dsPIC33E/PIC24E
device family supports a wide variety of PWM modes and is ideal for power
conversion/motor control applications. Some of the common applications include:
• AC-to-DC converters
• DC-to-DC converters
• AC and DC motors: BLDC, PMSM, ACIM, SRM, etc.
• Inverters
• Battery chargers
• Digital lighting
• Uninterrupted Power Supply (UPS)
• Power Factor Correction (PFC) (e.g., Interleaved PFC and Bridgeless PFC)
14.2 FEATURES
The High-Speed PWM module consists of the following major features:
• Up to seven PWM generators, each with an individual time base
• Two PWM outputs per PWM generator
• Individual period and duty cycle for each PWM output
• Duty cycle, dead time, phase shift and frequency resolution equal to the system clock
source (TOSC)
• Independent fault and current-limit inputs for up to 14 PWM outputs
• Redundant Output mode
• Independent Output mode (this feature is not available on all devices)
• Push-Pull Output mode
• Complementary Output mode
• Center-Aligned PWM mode
• Output override control
• Special Event Trigger
• PWM capture feature
• Prescaler for input clock
• ADC triggering with PWM
• Independent PWM frequency, duty cycle and phase shift changes
• Leading-Edge Blanking (LEB) functionality
• Dead time compensation
• Output clock chopping
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33E/PIC24E devices.
Please consult the note at the beginning of the “High-Speed PWM” chapter in the
current device data sheet to check whether this document supports the device you
are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-3
Section 14. High-Speed PWM
High-Speed PWM
14
14.3 CONTROL REGISTERS
The following registers control the operation of the High-Speed PWM module:
•PTCON: PWM Time Base Control Register
- Enables or disables the High-Speed PWM module
- Sets the Special Event Trigger for the ADC
- Enables or disables immediate period updates
- Selects the synchronizing source for the master time base
- Specifies synchronization settings
•PTCON2: PWM Clock Divider Select Register 2
Provides the clock prescaler to the PWM master time base
•PTPER: Primary Master Time Base Period Register
Provides the PWM time period value
•STCON: PWM Secondary Master Time Base Control Registe (1)
- Enables or disables immediate period updates based on the secondary master time base
- Selects the synchronization source for the secondary master time base
- Specifies the synchronization setting for secondary master time base control
• STCON2: PWM Secondary Clock Divider Select Register 2(1)
Provides the clock prescaler to the PWM secondary master time base
•STPER: Secondary Master Time Base Period Register(1)
Provides the secondary master time base period value
•MDC: PWM Master Duty Cycle Register
Provides the PWM master duty cycle value
•SEVTCMP: PWM Special Event Compare Register
Provides the compare value that is used to trigger the ADC module
•SSEVTCMP: PWM Secondary Special Event Compare Register(1)
Provides the compare value that is used to trigger the ADC module based on the
secondary master time base
•CHOP: PWM Chop Clock Generator Register
- Provides the chop clock frequency
- Enables or disables the chop clock generator
•PWMKEY: PWM Unlock Register(1)
Writes the unlock sequence to allow writes to the IOCONx and FCLCONx registers
•PWMCONx: PWM Control Register
- Enables or disables fault interrupt, current-limit interrupt and primary trigger interrupt
- Provides the interrupt status for fault interrupt, current-limit interrupt and primary trigger
interrupt
- Selects the type of time base (master time base or independent time base)
- Selects the type of duty cycle (master duty cycle or independent duty cycle)
- Controls Dead Time mode
- Enables or disables Center-Aligned mode
- Controls the external PWM Reset operation
- Enables or disables immediate updates of the duty cycle, phase offset, independent time
base period
•IOCONx: PWM I/O Control Register
- Enables or disables PWM pin control feature (PWM control or GPIO)
- Controls fault/current limit override values
- Enables PWMxH and PWMxL pin swapping
- Controls the PWMxH and PWMxL output polarity
- Controls the PWMxH and PWMxL output if any of the following modes is selected:
• Complementary mode
• Push-Pull mode
• True Independent mode
Note: Not all registers are available on all devices. Refer to the “High-Speed PWM”
chapter in the specific device data sheet for availability.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-11
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-11: PWMKEY: PWM Unlock Register(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWMKEY<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWMKEY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PWMKEY<15:0>: PWM Unlock bits
If the PWMLOCK Configuration bit is asserted (PWMLOCK = 1), the IOCONx and FCLCONx registers
are writable only after the proper sequence is written to the PWMKEY register. If the PWMLOCK
Configuration bit is deasserted (PWMLOCK = 0), the IOCONx and FCLCONx registers are writable at
all times. Refer to 14.5.3 “Write Protection” for further details of the unlock sequence.
Note 1: This register is implemented only in devices where the PWMLOCK Configuration bit is present in the
FOSCSEL Configuration register.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-15
Section 14. High-Speed PWM
High-Speed PWM
14
bit 5-4 FLTDAT<1:0>: State(2) for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(1)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If fault is active, FLTDAT<1> provides the state for PWMxH.
If fault is active, FLTDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
If current-limit is active, FLTDAT<1> provides the state for PWMxH.
If fault is active, FLTDAT<0> provides the state for PWMxL.
bit 3-2 CLDAT<1:0>: State(2) for PWMxH and PWMxL Pins if CLMOD is Enabled bits
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If current-limit is active, CLDAT<1> provides the state for PWMxH.
If current-limit is active, CLDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
The CLDAT<1:0> bits are ignored.
bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to PWMxL pin; PWMxL output signal is connected to PWMxH
pin
0 = PWMxH and PWMxL output signals pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0 = Output overrides via the OVRDAT<1:0> bits occur on next CPU clock boundary
Register 14-13: IOCONx: PWM I/O Control Register (Continued)
Note 1: These bits must not be changed after the PWM module is enabled (PTEN = 1).
2: State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example, if
FLTDAT<1> is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when a
fault occurs.
3: This feature is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific device
data sheet for availability.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-17
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-15: PDCx: PWM Generator Duty Cycle Register(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDCx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDCx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PDCx<15:0>: PWM Generator # Duty Cycle Value bits
Note 1: In Independent PWM mode, PMOD<1:0> (IOCONx<11:10>) = 11, the PDCx register controls the PWMxH
duty cycle only. In Complementary, Redundant and Push-Pull PWM modes (PMOD<1:0>
(IOCONx<11:0>) = 00 01, , or 10), the PDCx register controls the duty cycle of both the PWMxH and
PWMxL.
Register 14-16: PHASEx: PWM Primary Phase Shift Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PHASEx<15:0>: PWM Phase Shift Value or Independent Time Base Period bits for the PWM Generator
Note 1: If the ITB bit = 0 (PWMCONx<9>), the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00,
01 10, or ) PHASEx<15:0> = Phase shift value for PWMxH and PWMxL outputs
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11) PHASEx<15:0> = Phase
shift value for PWMxH only
2: If the ITB bit = 1(PWMCONx<9>), the following applies based on the mode of operation:
• Complementary, Redundant, and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00,
01 10, or ) PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11) PHASEx<15:0> = Independent
time base period for PWMxH only
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-28 © 2010-2011 Microchip Technology Inc.
14.5.4 Standard Edge-Aligned PWM
The standard edge-aligned PWM waveforms are illustrated in Figure 14-3. To create the
edge-aligned PWM, a timer or counter circuit counts upward from zero to a specified maximum
value, called Period. Another register contains the duty cycle value, which is constantly
compared with the timer value. When the timer or counter value is less than or equal to the duty
cycle value, the PWM output signal is asserted. When the timer value exceeds the duty cycle
value, the PWM signal is deasserted. When the timer value is greater than or equal to the period
value, the timer resets itself and the process repeats.
Figure 14-3: Standard Edge-Aligned PWM Mode
14.5.5 Center-Aligned PWM
The center-aligned PWM waveforms illustrated in Figure 14-4, align the PWM signals with
respect to a reference point so that half of the PWM signal occurs before the reference point and
the remaining half of the signal occurs after the reference point. The Center-Aligned mode is
enabled when the CAM bit (PWMCONx<2>) is set.
When operating in Center-Aligned mode, the effective PWM period is twice the value specified
in the PHASEx registers, because the independent time base counter in the PWM generator is
counting up and then counting down during the cycle. The up/down count sequence doubles the
effective PWM cycle period. This mode is used in many motor control applications.
Note: The Independent Time Base mode (ITB = 1) must be enabled to use the
Center-Aligned mode. If ITB = 0, the CAM bit is ignored.
PDC1
Period
Value
Timer
Value
Duty Cycle Match Timer Resets
Period
Duty Cycle
0
Period
TOFFTON
PWMxH
PWMxH
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-32 © 2010-2011 Microchip Technology Inc.
The Special Event Trigger output postscaler is cleared on these events:
• Any device Reset
• When PTEN = 0
Example 14-5: ADC Special Event Trigger Configuration
14.5.9 Independent PWM Time Base
Figure 14-6 illustrates the PWM functionality in the independent time base for devices that
support this feature.
Figure 14-6: Independent Time Base Block Diagrams
Each PWM generator can operate on:
• A shared time base for both the primary (PWMxH) and secondary (PWMxL) outputs
The independent time base periods for both PWM outputs (PWMxH and PWMxL) are
provided by the value in PWM Primary Phase Shift register (PHASEx).
• A dedicated time base for each of the primary (PWMxH) and secondary (PWMxL) outputs
The independent time base period for PWMxH output is provided by the value in the PWM
Primary Phase Shift register (PHASEx). The independent time base period for PWMxL
output is provided by the value in the PWM Secondary Phase Shift (SPHASEx) register.
The PHASEx and SPHASEx registers provide the time period value for the PWMx outputs
(PWMxH and PWMxL) in Independent Time Base mode.
/* ADC Special Event Trigger Configuration */
SEVTCMP = 1248; /* Special Event Trigger value set at 25% of the period value (4999)*/
PTCONbits.SEVTPS = 0; /* Special Event Trigger output postscaler set to 1:1 selection */
PTCONbits.SEIEN = 1; /* Special event interrupt is enabled */
while (PTCONbits.SESTAT == 1); /* Wait for special event interrupt status change */
PTMRx
PTPER
Equality Comparator
CLK
=
Reset
16
16
MUX
PHASEx
ITB (PWMCONx<9>)
0 1
15 0 15 0
15 0
STMRx
PTPER
Equality Comparator
CLK
=
Reset
16
16
MUX
SPHASEx
ITB (PWMCONx<9>)
0 1
15 0 15 0
15 0
ITB = 1, Controls PWMxH only ITB = 1, Controls PWMxL only
ITB = 0 0, Controls PWMxH and PWMxL ITB = , Not applicable
Note: The PTMRx and STMRx values are not readable to the user-assigned application.
Produktspecifikationer
| Varumärke: | Microchip |
| Kategori: | Inte kategoriserad |
| Modell: | dsPIC33EV256GM106 |
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