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PIC32 Family Reference Manual
DS61154C-page 34-2 © 2009-2012 Microchip Technology Inc.
34.1 INTRODUCTION
The PIC32 Controller Area Network (CAN) module implements the CAN Specification 2.0B,
which is used primarily in industrial and automotive applications. This asynchronous serial data
communication protocol provides reliable communication in an electrically noisy environment.
The PIC32 device family integrates up to two CAN modules. Figure 34-1 illustrates a typical CAN
bus topology.
Figure 34-1: Typical CAN Bus Network
The CAN module supports the following key features:
• Standards Compliance:
- Full CAN Specification 2.0B compliance
- Programmable bit rate up to 1 Mbps
• Message Reception and Transmission:
- 32 message FIFOs
- Each FIFO can have up to 32 messages for a total of 1024 messages
- FIFO can be a transmit message FIFO or a receive message FIFO
- User-defined priority levels for message FIFOs used for transmission
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for message filtering
- Automatic response to Remote Transmit Request (RTR)
- DeviceNet™ addressing support
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “Controller Area Network (CAN)”
chapter in the current device data sheet to check whether this document supports
the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
CAN
bus
CAN1
PIC®
with Integrated
ECAN
CAN
Transceiver
dsPIC33F
with Integrated
ECAN™
dsPIC30F
with Integrated
CAN
Transceiver
CAN Transceiver
CAN
Transceiver
CAN
CAN2
CAN
Transceiver
PIC32
PIC32 Family Reference Manual
DS61154C-page 34-4 © 2009-2012 Microchip Technology Inc.
34.2 CAN MESSAGE FORMATS
The CAN bus protocol uses asynchronous communication. Information is passed from the
transmitters to receivers in data frames, which are composed of byte fields that define the
contents of the data frame as illustrated in Figure 34-3.
Each frame begins with a Start of Frame (SOF) bit field and terminates with an End of Frame
(EOF) bit field. The SOF is followed by the Arbitration and Control fields, which identify the
message type, format, length and priority. This information allows each node on the CAN bus to
respond appropriately to the message. The Data field conveys the message content and is of
variable length, ranging from 0 bytes to 8 bytes. Error protection is provided by the Cyclic
Redundancy Check (CRC) and Acknowledgement (ACK) fields.
Figure 34-3: CAN Bus Message Frame
The CAN bus protocol supports four frame types:
•Data Frame – carries data from transmitter to the receivers
•Remote Frame – transmitted by a node on the bus, to request transmission of a data
frame with the same identifier from another node
•Error Frame – transmitted by any node when it detects an error
•Overload Frame – provides an extra delay between successive Data or remote frames
•Interframe Space – provides a separation between successive frames
The CAN Specification 2.0B defines two additional data formats:
•Standard Data Frame – intended for standard messages that use 11 identifier bits
•Extended Data Frame – intended for extended messages that use 29 identifier bits
There are three CAN Specification versions:
•2.0A – considers 29-bit identifier as error
• 2.0B Passive – ignores 29-bit identifier messages
•2.0B Active – handles both 11-bit and 29-bit identifiers
The PIC32 CAN module is compliant with the CAN Specification 2.0B, while providing enhanced
message filtering capabilities.
Note: For detailed information on the CAN protocol, refer to the Bosch CAN Bus
Specification 2.0B, which is available for download at:
http://www.semiconductors.bosch.de
S
O
F
E
O
F
ARBITRATION CONTROL DATA ACKCRC
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-5
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
34.2.1 Standard Data Frame
The standard data frame message begins with an SOF bit followed by a 12-bit Arbitration field
as illustrated in Figure 34-4. The Arbitration field contains an 11-bit identifier and RTR bit. The
identifier defines the type of information contained in the message, and is used by each receiving
node to determine if the message is of interest to it. The RTR bit distinguishes a data frame from
a remote frame. For a standard data frame, the RTR bit is clear.
Following the Arbitration field is a 6-bit Control field, which provides more information about the
contents of the message. The first bit in the Control field is an Identifier Extension (IDE) bit, which
distinguishes the message as either a standard or extended data frame. A standard data frame
is indicated by a dominant state (logic level ‘0’) during transmission of the IDE bit. The second
bit in the Control field is a reserved (RB0) bit, which is in the dominant state (logic level ‘0’). The
last four bits in the Control field represent the Data Length Code (DLC), which specifies the
number of data bytes present in the message.
The Data field follows the Control field. This field carries the message data – the actual payload
of the data frame. This field is of variable length, ranging from 0 bytes to eight bytes. The number
of bytes is user-selectable.
The Data field is followed by the CRC field, which is a 15-bit CRC sequence with one delimiter bit.
The Acknowledgement (ACK) field is sent as a recessive bit (logic level ‘1’), and is overwritten
as a dominant bit by any receiver that has received the data correctly. The message is
acknowledged by the receiver regardless of the result of the acceptance filter comparison.
The last field is the EOF field, which consists of seven recessive bits that indicate the end of
message.
Figure 34-4: Format of the Standard Data Frame
SID10 SID1
S
O
F
IDENTIFIER
11 Bits
R
T
R
I
D
E
RB0 DLC
4 Bits
DATA
8 Bytes
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID0
9/19/2006 - 9/26/2006
11-bit Identifier
Interframe Space
9/19/2006 - 9/26/2006 9/19/2006 - 9/26/2006
Data
9/19/2006 - 9/26/2006
9/19/2006 - 9/26/2006
9 - 9/26/2006
Frame Interframe Space
9/19/2006 - 9/26/2006
IDE is Dominant (Logical ‘0’)
RTR is Dominant (Logical ‘0’)
RB0 is Dominant (Logical ‘0’)
/19/
Arbitration
Field
Control
Field
Field
CRC
Field
ACK
Field
End-of-
PIC32 Family Reference Manual
DS61154C-page 34-6 © 2009-2012 Microchip Technology Inc.
34.2.2 Extended Data Frame
The extended data frame begins with an SOF bit followed by a 31-bit Arbitration field as
illustrated in Figure 34-5. The Arbitration field for the extended data frame contains 29 identifier
bits in two fields separated by a Substitute Remote Request (SRR) bit and an IDE bit. The SRR
bit determines if the message is a remote frame. SRR = 1 for extended data frames. The IDE bit
indicates the data frame type. For the extended data frame, IDE = 1.
The extended data frame Control field consists of seven bits. The first bit is the RTR. For the
extended data frame, RTR = 0. The next two bits, RB1 and RB0, are reserved bits that are in the
dominant state (logic level ‘0’). The last four bits in the Control field are the DLC, which specifies
the number of data bytes present in the message.
The remaining fields in an extended data frame are identical to a standard data frame.
Figure 34-5: Format of the Extended Data Frame
SID10 SID1
S
O
F
IDENTIFIER
11 Bits
S
R
R
I
D
E
R
T
R
DLC
4 BITS
CRC
16 BITS
ACK
2 BITS
EOF
7 BITS
IFS
3 BITS
SID0
Field
29-bit Identifier
9/19/2006 - 9/26/2006
Control
9/19/2006 - 9/26/2006
CRC
9/19/2006 - 9/26/2006
IDENTIFIER
18 BITS
EID17 EID1 EID0
R
B
1
R
B
0
IDE is Recessive (Logical ‘1’)
SRR is Recessive (Logical ‘1’)
RTR is Dominant (Logical ‘0’)
RB0 is Dominant (Logical ‘0’)
RB1 is Dominant (Logical ‘0’)
9/19/2006 - 9/26/2006
ACK End of
Frame
9/19/2006 - 9/26/20069/19/2006 - 9/26/2006
Data
DATA
8 Bytes
Arbitration
Field Field Field Field
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-7
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
34.2.3 Remote Frame
A node expecting to receive data from another node can initiate transmission of the respective
data by the source node, by sending a remote frame. A remote frame can be in standard format
(Figure Figure 34-6) or the extended format ( 34-7).
A Remote frame is similar to a data frame, with the following exceptions:
• The RTR bit is recessive (RTR = 1)
• There is no Data field (DLC = 0)
Figure 34-6: Format of the Standard Remote Frame
Figure 34-7: Format of the Extended Remote Frame
SID10 SID1
S
O
F
IDENTIFIER
11 Bits
R
T
R
I
D
E
DLC
4 Bits
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID0
11-bit Identifier
RB0
IDE is Dominant (Logical ‘0’)
RTR is Recessive (Logical ‘1’)
RB0 is Dominant (Logical ‘0’)
Arbitration Field Control Field CRC Field ACK Field End of Frame
SID10 SID0
S
O
F
IDENTIFIER
11 Bits
S
R
R
I
D
E
R
T
R
DLC
4 Bits
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID1
Arbitration Field
29-bit Identifier
Control Field CRC Field
IDENTIFIER
18 Bits
EID17 EID1 EID0
R
B
1
R
B
0
IDE is Recessive (Logical ‘1’)
SRR is Recessive (Logical ‘1’)
RTR is Recessive (Logical ‘1’)
RB0 is Dominant (Logical ‘0’)
RB1 is Dominant (Logical ‘0’)
ACK Field
End of
Frame
PIC32 Family Reference Manual
DS61154C-page 34-8 © 2009-2012 Microchip Technology Inc.
34.2.4 Error Frame
An error frame is generated by any node that detects a bus error. An error frame consists of an
Error Flag field followed by an Error Delimiter field. The Error Delimiter consists of eight recessive
bits and allows the bus nodes to restart communication cleanly after an error has occurred. There
are two types of error flag fields, depending on the error status of the node that detects the error:
•Error Active Flag – contains six consecutive dominant bits, which forces all other nodes
on the network to generate Error Echo Fags, thereby resulting in a series of 6 to 12
dominant bits on the bus
•Error Passive Flag – contains six consecutive recessive bits, with the result that unless
the bus error is detected by the transmitting node, the transmission of an Error Passive
Flag will not affect the communication of any other node on the network
34.2.5 Overload Frame
An Overload Frame can be generated by a node either when a dominant bit is detected during
Interframe Space or when a node is not ready to receive the next message (for example, if it is
still reading the previous received message). An Overload Frame has the same format as an
Error Frame with an Active Error Flag, but can only be generated during Interframe Space. It
consists of an Overload Fag field with six dominant bits followed by an Overload Delimiter field
with eight recessive bits. A node can generate a maximum of two sequential overload frames to
delay the start of the next message.
34.2.6 Interframe Space
Interframe Space separates successive frames being transmitted on the CAN bus. It consists of
at least three recessive bits, referred to as intermission. The Interframe Space allows nodes time
to internally process the previously received message before the start of the next frame. If the
transmitting node is in the Error Passive state, an additional eight recessive bits will be inserted
in the Interframe Space before any other message is transmitted by the node. This period is
called a Suspend Transmit field and allows time for other transmitting nodes to take control of the
bus.
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-9
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
34.3 CAN REGISTERS
The CAN module registers can be classified by their function into the following groups:
• Module and CAN bit rate Configuration registers
• Interrupt and Status registers
• Mask and Filter Configuration registers
• FIFO Control registers
34.3.1 Module and CAN Bit Rate Configuration Registers
•CiCON: CAN Module Control Register
This register is used to set up the CAN module operational mode and DeviceNet
addressing.
•CiCFG: CAN Baud Rate Configuration Register
This register contains control bits to set the period of each time quantum, using the baud rate
prescaler, and specifies Synchronization Jump Width (SJW) in terms of time quanta. It is
also used to program the number of time quanta in each CAN bit segment, including the
propagation and phase segments 1 and 2.
34.3.2 Interrupt and Status Registers
•CiINT: CAN Interrupt Register
This register allows various CAN module interrupt sources to be enabled and disabled. It
also contains interrupt status flags.
•CiVEC: CAN Interrupt Code Register
This register provides status bits which provide information on CAN module interrupt source
and message filter hits. These values can be used to implement a jump table for handling
different cases.
•CiTREC: CAN Transmit/Receive Error Count Register
This register provides information on Transmit and Receive Error Counter values. It also has
bits which indicate various warning states.
•CiFSTAT: CAN FIFO Status Register
This register contains interrupt status flag for all the FIFOs.
•CiRXOVF: CAN Receive FIFO Overflow Status Register
This register contains overflow interrupt status flag for all the FIFOs.
•CiTMR: CAN TImer Register
This register contains CAN Message Timestamp timer and a Prescaler.
34.3.3 Mask and Filter Configuration Registers
•CiRXMn: CAN Acceptance Filter Mask n Register (n = 0, 1, 2 or 3)
These registers allow the configuration of the filter masks. A total of four masks are
available.
•CiFLTCON0: CAN Filter Control Register 0 through CiFLTCON7: CAN Filter Control
Register 7
These registers allow the association of FIFO and Masks with a filter. A Filter can be
associated with any one mask. It also contains a filter enable/disable bit.
•CiRXFn: CAN Acceptance Filter n Register 7 (n = 0 through 31)
These registers specify the filter to be applied to the received message. A total of 32 filters
are available.
Note: The ‘i’ shown in the register identifier denotes CAN1 or CAN2.
PIC32 Family Reference Manual
DS61154C-page 34-10 © 2009-2012 Microchip Technology Inc.
34.3.4 CAN Module Control Registers
•CiFIFOBA: CAN Message Buffer Base Address Register
This register holds the base (start) address of the CAN message buffer area. This is a
physical address.
•CiFIFOCONn: CAN FIFO Control Register (n = 0 through 31)
These registers allow the control and configuration of CAN Message FIFOs.
•CiFIFOINTn: CAN FIFO Interrupt Register (n = 0 through 31)
These registers allow the individual FIFO interrupt sources to be enabled or disabled. They
also contain interrupt status bits.
•CiFIFOUAn: CAN FIFO User Address Register (n = 0 through 31)
These registers provide the addr the CAN message FIFO from ess of the memory location in
where the next message can be read or where the next message should be written to.
•CiFIFOCIn: CAN Module Message Index Register (n = 0 through 31)
These registers provide the message buffer index (in the message FIFO) of the next
message that the CAN module will transmit or where the next received message will be
saved.
Table 34-1 provides a summary of all CAN-related registers. Corresponding registers appear
after the summary, followed by a detailed description of each register. All unimplemented
registers and/or bits within a register read as zeros.
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-11
Section 34. Controller Area Network (CAN)
Controller Area
Network (CAN)
34
Table 34-1: CAN Controller Register Summary
Name Bit
Range
Bit
31/2315/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
CiCON(1) 31:24 — — — — ABAT REQOP<2:0>
23:16 OPMOD<2:0> CANCAP — — — —
15:8 ON — — — — —SIDLE CANBUSY
7:0 — — — DNCNT<4:0>
CiCFG (1) 31:24 — — — — — — — —
23:16 — — — —WAKFIL SEG2PH<2:0>
15:8 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0>
7:0 SJW<1:0> BRP<5:0>
CiINT (1) 31:24 IVRIE WAKIE CERRIE SERRIE RBOVIE — — —
23:16 — — — — MODIE CTMRIE RBIE TBIE
15:8 IVRIF WAKIF CERRIF SERRIF RBOVIF — — —
7:0 — — — — MODIF CTMRIF RBIF TBIF
CiVEC(1) 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — FILHIT<4:0>
7:0 — ICODE<6:0>
CiTREC(1) 31:24 — — — — — — — —
23:16 — — TXBO TXBP RXBP TXWARN RXWARN EWARN
15:8 TERRCNT<7:0>
7:0 RERRCNT<7:0>
CiFSTAT(1) 31:24 FIFOIP31 FIFOIP29 FIFOIP28 FIFOIP26 FIFOIP25FIFOIP30 FIFOIP27 FIFOIP24
23:16 FIFOIP23 FIFOIP21 FIFOIP20 FIFOIP18 FIFOIP17FIFOIP22 FIFOIP19 FIFOIP16
15:8 FIFOIP15 FIFOIP13 FIFOIP12FIFOIP14 FIFOIP11 FIFOIP8FIFOIP10 FIFOIP9
7:0 FIFOIP7 FIFOIP4 FIFOIP1FIFOIP6 FIFOIP5 FIFOIP3 FIFOIP2 FIFOIP0
CiRXOVF(1) 31:24 RXOVF31 RXOVF24RXOVF30 RXOVF29 RXOVF28 RXOVF25RXOVF27 RXOVF26
23:16 RXOVF23 RXOVF16RXOVF22 RXOVF21 RXOVF20 RXOVF17RXOVF19 RXOVF18
15:8 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF8RXOVF10 RXOVF9
7:0 RXOVF7 RXOVF4 RXOVF1RXOVF6 RXOVF5 RXOVF3 RXOVF2 RXOVF0
CiTMR(1) 31:24 CANTS<15:8>
23:16 CANTS<7:0>
15:8 CANTSPRE<15:8>
7:0 CANTSPRE<7:0>
CiRXM0(1) 31:24 SID<10:3>
23:16 SID<2:0> MIDE-— — EID<17:16>
15:8 EID<15:8>
7:0 EID<7:0>
CiRXM1(1) 31:24 SID<10:3>
23:16 SID<2:0> MIDE-— — EID<17:16>
15:8 EID<15:8>
7:0 EID<7:0>
CiRXM2(1) 31:24 SID<10:3>
23:16 SID<2:0> MIDE-— — EID<17:16>
15:8 EID<15:8>
7:0 EID<7:0>
Legend: ‘—’ = unimplemented; read as ‘0’.
Note 1: This register has an associated Clear, Set, and Invert register at an offset of 0x4, 0x8, or 0xC bytes, respectively. These registers have
the same name with CLR, SET, or INV appended to the end of the register name (For example, CiCONCLR). Writing a ‘1’ to any bit
position in these registers will clear, set, or invert valid bits in the associated register. Reads from these registers should be ignored.
PIC32 Family Reference Manual
DS61154C-page 34-14 © 2009-2012 Microchip Technology Inc.
Register 34-1: CiCON: CAN Module Control Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24 U-0 U-0U-0 U-0 S/HC-0 R/W-1 R/W-0 R/W-0
— — — — ABAT REQOP<2:0>
23:16 R-1 R-0 R-0 R/W-0 U-0 U-0 U-0 U-0
OPMOD<2:0> CANCAP — — — —
15:8 R/W-0 U-0 U-0R/W-0 U-0 R-0 U-0 U-0
ON(1) — — — — —SIDLE CANBUSY
7:0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DNCNT<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27 ABAT: Abort All Pending Transmissions bit
1 = Signal all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions aborted
bit 26-24 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved; do not use
101 = Reserved; do not use
100 = Set Configuration mode
011 = Set Listen-Only mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 23-21 OPMOD<2:0>: Operation Mode Status bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen-Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit
1 = CANTMR value is stored on valid message reception and is stored with the message
0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power
bit 19-16 Unimplemented: Read as ‘0’
bit 15 ON: CAN On bit(1)
1 = CAN module is enabled
0 = CAN module is disabled
bit 14 Unimplemented: Read as ‘0’
Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.
Produktspecifikationer
| Varumärke: | Microchip |
| Kategori: | Inte kategoriserad |
| Modell: | PIC32MX530F128H |
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