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Section 22. 12-bit High-Speed Successive Approximation

This section of the manual contains the following major topics:

22.1 Introduction .................................................................................................................. 22-2

22.2 Control Registers ......................................................................................................... 22-6

22.3 ADC Operation........................................................................................................... 22-61

22.4 ADC Module Configuration ........................................................................................ 22-65

22.5 Additional ADC Functions .......................................................................................... 22-85

22.6 Interrupts.................................................................................................................. 22-108

22.7 Operation During Power-Saving Modes .................................................................. 22-114

22.8 Effects of Reset........................................................................................................ 22-116

22.9 Transfer Function..................................................................................................... 22-116

22.10 ADC Sampling Requirements.................................................................................. 22-117

22.11 Connection Considerations...................................................................................... 22-117

22.12 Related Application Notes........................................................................................ 22-118

22.13 Revision History ....................................................................................................... 22-119

PIC32 Family Reference Manual

22.1 INTRODUCTION

The PIC32 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital

Converter (ADC) includes the following features:

• 12-bit resolution

• Up to eight ADC modules with dedicated Sample and Hold (S&H) circuits (see Note 1)

• Two dedicated ADC modules can be combined in Turbo mode to provide double

conversion rate

• Single-ended and/or differential inputs

• Can operate during Sleep mode

• Supports touch sense applications

• Up to six digital comparators

• Up to six digital filters supporting two modes:

- Oversampling mode

- Averaging mode

• FIFO and DMA engine for dedicated ADC modules (see Note 2)

• Early interrupt generation resulting in faster processing of converted data

• Designed for motor control, power conversion, and general purpose applications

The dedicated ADC modules use a single input (or its alternate) and is intended for high-speed

and precise sampling of time-sensitive or transient inputs, whereas the shared ADC module

incorporates a multiplexer on the input to facilitate a larger group of inputs, with slower sampling,

and provides flexible automated scanning option through the input scan logic.

For each ADC module, the analog inputs are connected to the S&H capacitor. The clock,

sampling time, and output data resolution for each ADC module can be set independently. The

ADC module performs the conversion of the input analog signal based on the configurations set

in the registers. When conversion is complete, the final result is stored in the result buffer for the

specific analog input and is passed to the digital filter and digital comparator if configured to use

data from this particular sample.

A simplified block diagram of the ADC module is illustrated in Figure 22-1.

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device, this manual section may not apply to all

PIC32 devices.

Please refer to the note at the beginning of the “ADC” chapter in the current device

data sheet to check whether this document supports the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Note 1: Depending on the device, the 12-bit High-Speed SAR ADC has up to seven

dedicated ADC modules and one shared ADC module. Throughout this chapter,

the diagrams and code examples refer to a device with seven dedicated ADC

modules (ADC0-ADC6) and one shared ADC (ADC7). Please consult the “ADC”

chapter in the specific device data sheet to determine which ADC modules are

available for your device.

2: This feature is not available on all devices. Refer to the “ADC” chapter in the

specific device data sheet to determine availability.

3: Prior to enabling the ADC module, the user application must copy the ADC

calibration data (DEVADCx) from the Configuration memory into the ADC

Configuration registers (ADC0CFG-ADC7CFG). Refer to the “ADC” chapter in the

specific device data sheet for more information.

Section 22. 12-bit High-Speed SAR ADC

Figure 22-1: ADC Block Diagram

Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features

are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the

actual ANx selections, ADC module availability, and the specific FIFO and DMA features.

ADC0

ADC7

REF

+ V

REF

VREFSEL<2:0>

REFH

REFL

ADCSEL<1:0>

CONCLKDIV<5:0>

FRC PBCLK

ADCDIV<6:0>

(ADCxTIME<22:16>)

ADCDIV<6:0>

(ADCCON2<6:0>)

AD0

-T

AD6

AD7

ADDATA0

…...

ADDATA63

(Dedicated

ADC)

(Dedicated

ADC)

FIFO

DMA

Digital Filter

Digital Comparator Interrupt/Event

Capacitive Voltage

Divider (CVD) Interrupt/Event

Triggers,

Turbo Channel,

Scan Control Logic

Trigger

Status and Control

Registers

ADC6

SH0ALT<1:0>

(ADCTRGMODE<17:16>)

ANx

REFL

DIFFx<1>

(ADCIMCONx<x>)

ANa

AN1

REFL

DIFF1<1>

(ADCIMCON1<3>)

SH6ALT<1:0>

(ADCTRGMODE<29:28>)

ANx

REFL

DIFFx<1>

(ADCIMCONx<x>)

AN49

CTMU

BAT

AN48

AN7

CVD

Capacitor

CLK

ANb

ANc

ANd

ANb

ANc

ANd

SYSTEMBUS

ANa

Interrupt

Data

PIC32 Family Reference Manual

Figure 22-2: FIFO Block Diagram

FEN

(ADCFSTAT<31>

FIFO

(Depth Device Dependent)

ADCFIFO DATA<31:0>

ADCID<2:0>

ADCFSTAT<2:0> ADCx ID

ADCx ID Converted Data

ADC6

ADC6EN

(ADCFSTAT<30>)

ADC5

ADC5EN

(ADCFSTAT<29>)

ADC0

ADC0EN

(ADCFSTAT<24>)

If data

available in

FIFO

FRDY

ADCFSTAT<22>

FIEN

(ADCFSTAT<23>

Interrupt

FCNT<7:0>

ADCFSTAT<15:8>

(Number of data in FIFO)

Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features

are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the

actual ANx selections, ADC module availability, and the specific FIFO and DMA features.

PIC32 Family Reference Manual

22.2 CONTROL REGISTERS

The PIC32 12-bit High-Speed SAR ADC module has the following Special Function Registers

(SFRs):

•ADCCON1: ADC Control Register 1

This register controls the basic operation of all ADC modules, including behavior in Sleep

and Idle modes, and data formatting. This register also specifies the vector shift amounts for

the Interrupt Controller. Additional ADCCON1 functions include controlling the Turbo feature

of the ADC, the RAM buffer length in DMA mode, and Capacitive Voltage Division (CVD).

•ADCCON2: ADC Control Register 2

This register controls the reference selection for all ADC modules, the sample time for the

shared ADC module, interrupt enable for reference, early interrupt selection, and clock

division selection for the shared ADC.

•ADCCON3: ADC Control Register 3

This register enables ADC clock selection, enables/disables the digital feature for the

dedicated and shared ADC modules and controls the manual (software) sampling and

conversion.

•ADCTRGMODE: ADC Triggering Mode for Dedicated ADC Register

This register has selections for alternate analog inputs and includes trigger settings for the

dedicated ADC modules.

•ADCIMCON1: ADC Input Mode Control Register 1 through

ADCIMCON4: ADC Input Mode Control Register 4

These registers enable the user to select between single-ended and differential operation

as well as select between signed and unsigned data format.

•ADCGIRQEN1: ADC Global Interrupt Enable Register 1 and

ADCGIRQEN2: ADC Global Interrupt Enable Register 2

These registers specify which of the individual input conversion interrupts can generate the

global ADC interrupt.

•ADCCSS1: ADC Common Scan Select Register 1 and

ADCCSS2: ADC Common Scan Select Register 2

These registers specify the analog inputs to be scanned by the common scan trigger.

•ADCDSTAT1: ADC Data Ready Status Register 1 and

ADCDSTAT2: ADC Data Ready Status Register 2

These registers contain the interrupt status of the individual analog input conversions. Each

bit represents the data-ready status for its associated conversion result.

•ADCCMPENx: ADC Digital Comparator ‘x’ Enable Register (‘x’ = 1 through 6)

These registers select which analog input conversion results will be processed by the digital

comparator.

•ADCCMPx: ADC Digital Comparator ‘x’ Limit Value Register (‘x’ = 1 through 6)

These registers contain the high and low digital comparison values for use by the digital

comparator.

•ADCFLTRx: ADC Digital Filter ‘x’ Register (‘x’ = 1 through 6)

These registers provide control and status bits for the oversampling filter accumulator, and

also includes the 16-bit filter output data.

•ADCTRG1: ADC Trigger Source 1Register

This register controls the trigger source selection for AN0 through AN3 analog inputs.

•ADCTRG2: ADC Trigger Source 2 Register

This register controls the trigger source selection for AN4 through AN7 analog inputs.

•ADCTRG3: ADC Trigger Source 3 Register

This register controls the trigger source selection for AN8 through AN11 analog inputs.

•ADCTRG4: ADC Trigger Source 4 Register

This register controls the trigger source selection for AN12 through AN15 analog inputs.

•ADCTRG5: ADC Trigger Source 5 Register

This register controls the trigger source selection for AN16 through AN19 analog inputs.

Table 22-1 provides a summary of all ADC Special Function Registers (SFRs). Corresponding registers

include a detailed description of each bit. Depending on the device, functionality will vary. Refer to the “A

data sheet to determine which registers are available for your device.

Table 22-1: ADC SFR Summary

Range Bit 31/15 Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9 Bit 24/8 Bit 23/7 Bit 22/6 Bit 21/5 Bit 20/4 B

ADCCON1

31:16 TRBEN TRBERR TRBMST<2:0> TRBSLV<2:0> FRACT SELRES<1:0>

15:0 ON — SIDL AICPMPEN CVDEN FSSCLKEN FSPBCLKEN — — IRQVS<2:0> ST

ADCCON2

31:16 BGVRRDY REFFLT EOSRDY CVDCPL<2:0> SAMC<9:0>

15:0 BGVRIEN REFFLTIEN EOSIEN ADCEIOVR ECRIEN ADCEIS<2:0> — ADC

ADCCON3

31:16 ADCSEL<1:0> CONCLKDIV<5:0> DIGEN7 DIGEN6 DIGEN5 DIGEN4 D

15:0 VREFSEL<2:0> TRGSUSP UPDIEN UPDRDY SAMP RQCNVRT GLSWTRG GSWTRG

ADCTRGMODE

31:16 — — SH6ALT<1:0> SH5ALT<1:0> SH4ALT<1:0> SH3ALT<1:0> SH2ALT<1:0>

15:0 — STRGEN6 STRGEN5 STRGEN4 STRGEN3 STRGEN2 STRGEN1 STRGEN0 — SSAMPEN6 SSAMPEN5 SSAMPEN4 SS

ADCIMCON1

31:16 DIFF15 SIGN15 DIFF14 SIGN14 DIFF13 SIGN13 DIFF12 SIGN12 DIFF11 SIGN11 DIFF10 SIGN10

15:0 DIFF7 SIGN7 DIFF6 SIGN6 DIFF5 SIGN5 DIFF4 SIGN4 DIFF3 SIGN3 DIFF2 SIGN2 D

ADCIMCON2

31:16 DIFF31 SIGN31 DIFF30 SIGN30 DIFF29 SIGN29 DIFF28 SIGN28 DIFF27 SIGN27 DIFF26 SIGN26 D

15:0 DIFF23 SIGN23 DIFF22 SIGN22 DIFF21 SIGN21 DIFF20 SIGN20 DIFF19 SIGN19 DIFF18 SIGN18 D

ADCIMCON3

31:16 DIFF47 SIGN47 DIFF46 SIGN46 DIFF45 SIGN45 DIFF44 SIGN44 DIFF43 SIGN43 DIFF42 SIGN42 D

15:0 DIFF39 SIGN39 DIFF38 SIGN38 DIFF37 SIGN37 DIFF36 SIGN36 DIFF35 SIGN35 DIFF34 SIGN34 D

ADCIMCON4

31:16 DIFF63 SIGN63 DIFF62 SIGN62 DIFF61 SIGN61 DIFF60 SIGN60 DIFF59 SIGN59 DIFF58 SIGN58 D

15:0 DIFF55 SIGN55 DIFF54 SIGN54 DIFF53 SIGN53 DIFF52 SIGN52 DIFF51 SIGN51 DIFF50 SIGN50 D

ADCGIRQEN1

31:16 AGIEN31 AGIEN30 AGIEN29 AGIEN28 AGIEN27 AGIEN26 AGIEN25 AGIEN24 AGIEN23 AGIEN22 AGIEN21 AGIEN20 A

15:0 AGIEN15 AGIEN14 AGIEN13 AGIEN12 AGIEN11 AGIEN10 AGIEN9 AGIEN8 AGIEN7 AGIEN6 AGIEN5 AGIEN4 A

ADCGIRQEN2

31:16 AGIEN63 AGIEN62 AGIEN61 AGIEN60 AGIEN59 AGIEN58 AGIEN57 AGIEN56 AGIEN55 AGIEN54 AGIEN53 AGIEN52 A

15:0 AGIEN47 AGIEN46 AGIEN45 AGIEN44 AGIEN43 AGIEN42 AGIEN41 AGIEN40 AGIEN39 AGIEN38 AGIEN37 AGIEN36 A

ADCCSS1

31:16 CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 CSS23 CSS22 CSS21 CSS20 C

15:0 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4

ADCCSS2

31:16 CSS63 CSS62 CSS61 CSS60 CSS59 CSS58 CSS57 CSS56 CSS55 CSS54 CSS53 CSS52 C

15:0 CSS47 CSS46 CSS45 CSS44 CSS43 CSS42 CSS41 CSS40 CSS39 CSS38 CSS37 CSS36 C

ADCDSTAT1

31:16 ARDY31 ARDY30 ARDY29 ARDY28 ARDY27 ARDY26 ARDY25 ARDY24 ARDY23 ARDY22 ARDY21 ARDY20 A

15:0 ARDY15 ARDY14 ARDY13 ARDY12 ARDY11 ARDY10 ARDY9 ARDY8 ARDY7 ARDY6 ARDY5 ARDY4 A

ADCDSTAT2

31:16 ARDY63 ARDY62 ARDY61 ARDY60 ARDY59 ARDY58 ARDY57 ARDY56 ARDY55 ARDY54 ARDY53 ARDY52 A

15:0 ARDY47 ARDY46 ARDY45 ARDY44 ARDY43 ARDY42 ARDY41 ARDY40 ARDY39 ARDY38 ARDY37 ARDY36 A

ADCCMPENx

‘x’ = 1-6

31:16 CMPE31 CMPE30 CMPE29 CMPE28 CMPE27 CMPE26 CMPE25 CMPE24 CMPE23 CMPE22 CMPE21 CMPE20 C

15:0 CMPE15 CMPE14 CMPE13 CMPE12 CMPE11 CMPE10 CMPE9 CMPE8 CMPE7 CMPE6 CMPE5 CMPE4 C

ADCCMPx

‘x’ = 1-6

31:16 DCMPHI<15:0>

15:0 DCMPLO<15:0>

ADCFLTRx

‘x’ = 1-6

31:16 AFEN DATA16EN DFMODE OVRSAM<2:0> AFGIEN AFRDY — — —

15:0 FLTRDATA<15:0>

ADCTRG1

31:16 — — — —— TRGSRC3<4:0> —

15:0 — — — —— TRGSRC1<4:0> —

ADCTRG2

31:16 — — — —— TRGSRC7<4:0> —

15:0 — — — —— TRGSRC5<4:0> —

ADCTRG3

31:16 — — — TRGSRC11<4:0> —— —

15:0 — — — —— TRGSRC9<4:0> —

ADCTRG4

31:16 — — — TRGSRC15<4:0> —— —

15:0 — — — —— TRGSRC13<4:0> —

ADCTRG5

31:16 — — — TRGSRC19<4:0> —— —

15:0 — — — —— TRGSRC17<4:0> —

Note 1: Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory-programmed DEVADCx Flash register

registers.

Section 22. 12-bit High-Speed SAR ADC

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when the device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 AICPMPEN: Analog Input Charge Pump Enable bit

1 = Analog input charge pump is enabled (default)

0 = Analog input charge pump is disabled

bit 11 CVDEN: Capacitive Voltage Division Enable bit

1 = CVD operation is enabled

0 = CVD operation is disabled

bit 10 FSSCLKEN: Fast Synchronous System Clock to ADC Control Clock bit

1 = Fast synchronous system clock to ADC control clock is enabled

0 = Fast synchronous system clock to ADC control clock is disabled

bit 9 FSPBCLKEN: Fast Synchronous Peripheral Clock to ADC Control Clock bit

1 = Fast synchronous peripheral clock to ADC control clock is enabled

0 = Fast synchronous peripheral clock to ADC control clock is disabled

bit 8-7 Unimplemented: Read as ‘0’

bit 6-4 IRQVS<2:0>: Interrupt Vector Shift bits

To determine interrupt vector address, this bit specifies the amount of left shift done to the ARDYx status

bits in the ADCDSTAT1 and ADCDSTAT2 registers, prior to adding with the ADCBASE register (see

22.6.2 “ADC Base Register (ADCBASE) Usage” for more information).

Interrupt Vector Address = Read Value of ADCBASE = Value written to ADCBASE + x << IRQVS<2:0>,

where ‘x’ is the smallest active input ID from the ADCDSTAT1 or ADCDSTAT2 registers (which has highest

priority).

111 = Shift x left 7 bit position

110 = Shift x left 6 bit position

101 = Shift x left 5 bit position

100 = Shift x left 4 bit position

011 = Shift x left 3 bit position

010 = Shift x left 2 bit position

001 = Shift x left 1 bit position

000 = Shift x left 0 bit position

bit 3 STRGLVL: Scan Trigger High Level/Positive Edge Sensitivity bit

1= Scan trigger is high level sensitive. Once STRIG mode is selected (TRGSRCx<4:0> in the ADCTRGx

0= Scan trigger is positive edge sensitive. Once STRIG mode is selected (TRGSRCx<4:0> in the

ADCTRGx register), only a single scan trigger will be generated, which will complete the scan of all

selected analog inputs.

bit 2-0 DMABL<2:0>: DMA Buffer Length Size bits

111 = Allocates 128 locations in RAM to each analog input

110 = Allocates 64 locations in RAM to each analog input

101 = Allocates 32 locations in RAM to each analog input

100 = Allocates 16 locations in RAM to each analog input

011 = Allocates 8 locations in RAM to each analog input

010 = Allocates 4 locations in RAM to each analog input

001 = Allocates 2 locations in RAM to each analog input

000 = Allocates 1 location in RAM to each analog input

Note: Since each output data is 16-bit wide, one location consists of 2 bytes.

Section 22. 12-bit High-Speed SAR ADC

bit 14 REFFLTIEN: Band Gap/V

REF

Voltage Fault Interrupt Enable bit

1 = Interrupt will be generated when the REFFLT bit is set

0 = No interrupt is generated when the REFFLT bit is set

bit 13 EOSIEN: End of Scan Interrupt Enable bit

1 = Interrupt will be generated when EOSRDY bit is set

0 = No interrupt is generated when the EOSRDY bit is set

bit 12 ADCEIOVR: Early Interrupt Request Override bit

1 = Early interrupt generation is overridden and interrupt generation is controlled by the ADCGIRQEN1

and ADCGIRQEN2 registers

0 = Early interrupt generation is not overridden and interrupt generation is controlled by the ADCEIEN1

and ADCEIEN2 registers

bit 11 ECRIEN: External Conversion Request Interface Enable bit

1 = Enables ADC conversion start from external module (such as PTG)

0 = External modules cannot start ADC conversion

bit 10-8 ADCEIS<2:0>: Shared ADC Early Interrupt Select bits

These bits select the number of clocks (T

)

prior to the arrival of valid data that the associated interrupt

is generated.

111 = The data ready interrupt is generated 8 ADC clocks prior to end of conversion

110 = The data ready interrupt is generated 7 ADC clocks prior to end of conversion

•

001 = The data ready interrupt is generated 2 ADC module clocks prior to end of conversion

000 = The data ready interrupt is generated 1 ADC module clock prior to end of conversion

Note: All options are available when the selected resolution, set by the SELRES<1:0> bits

(ADCCON1<22:21>), is 12-bit or 10-bit. For a selected resolution of 8-bit, options from ‘000’ to

‘101’ are valid. For a selected resolution of 6-bit, options from ‘000’ to ‘011’ are valid.

bit 7 Unimplemented: Read as ‘0’

bit 6-0 ADCDIV<6:0>: Shared ADC Clock Divider bits

1111111 = 254 * T

= T

•

0000011 = 6 * T

= T

0000010 = 4 * T

= T

0000001 = 2 * T

= T

0000000 = Reserved

The ADCDIV<6:0> bits divide the ADC control clock (T

) to generate the clock for the Shared ADC (T

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCSEL<1:0> CONCLKDIV<5:0>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIGEN7

(5)

DIGEN6

(5)

DIGEN5

(5)

DIGEN4

(5)

DIGEN3

(5)

DIGEN2

(5)

DIGEN1

(5)

DIGEN0

(5)

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R/W-0 R-0, HS, HC

VREFSEL<2:0> TRGSUSP UPDIEN UPDRDY SAMP

(1,2,3,4)

RQCNVRT

7:0

R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GLSWTRG GSWTRG ADINSEL<5:0>

(5)

Legend: HC = Hardware Set HS = Hardware Cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 ADCSEL<1:0>: Analog-to-Digital Clock Source (T

CLK

) bits

Refer to the “12-bit High-Speed Successive Approximation Register (SAR)” chapter in the specific

device data sheet for the ADC Clock source selections.

bit 29-24 CONCLKDIV<5:0>: Analog-to-Digital Control Clock (T

) Divider bits

111111 = 126 * T

CLK

= T

•

000011 = 6 * T

CLK

= T

000010 = 4 * T

CLK

= T

000001 = 2 * T

CLK

= T

000000 = T

CLK

= T

bit 23 DIGEN7: ADC7 Digital Enable bit

(5)

1 = ADC7 is digital enabled

0 = ADC7 is digital disabled

bit 22 DIGEN6: ADC6 Digital Enable bit

(5)

1 = ADC6 is digital enabled

0 = ADC6 is digital disabled

bit 21 DIGEN5: ADC5 Digital Enable bit

(5)

1 = ADC5 is digital enabled

0 = ADC5 is digital disabled

bit 20 DIGEN4: ADC4 Digital Enable bit

(5)

1 = ADC4 is digital enabled

0 = ADC4 is digital disabled

Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the

bit is cleared. Also, usage of the SAMP bit will cause settings of the SAMC<9:0> bits (ADCCON2<25:16>)

to be ignored.

2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC. All Class 1 analog

inputs are not affected by the SAMP bit.

3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit

and only after setting the RQCNVRT bit to start the analog-to-digital conversion.

4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits and

STRGSRC<4:0> bits should be set to ‘00000’ to disable all external hardware triggers and prevent them

from interfering with the software-controlled sampling command signal SAMP and with the

software-controlled trigger RQCNVRT.

5: Depending on the device, the function will vary. Refer to the “ADC” chapter in the specific device data

sheet to determine the function that is available for your device.

PIC32 Family Reference Manual

bit 8 RQCNVRT: Individual ADC Input Conversion Request bit

This bit and its associated ADINSEL<5:0> bits enable the user to individually request an analog-to-digital

conversion of an analog input through software.

1 = Trigger the conversion of the selected ADC input as specified by the ADINSEL<5:0> bits

0 = Do not trigger the conversion

Note: This bit is automatically cleared in the next ADC clock cycle.

bit 7 GLSWTRG: Global Level Software Trigger bit

1 = Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal, either

through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0>

bits in the ADCCON1 register

0 = Do not trigger an analog-to-digital conversion

bit 6 GSWTRG: Global Software Trigger bit

1 = Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal, either

through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0>

bits in the ADCCON1 register

0 = Do not trigger an analog-to-digital conversion

Note: This bit is automatically cleared in the next ADC clock cycle.

bit 5-0 ADINSEL<5:0>: Analog Input Select bits

(5)

These bits select the analog input to be converted when the RQCNVRT bit is set, where, MAX_AN_INPUT

is the maximum analog inputs available on the device.

MAX_AN_INPUT + 4 = Device dependent (see Note 5)

MAX_AN_INPUT + 3 = Device dependent (see Note 5)

MAX_AN_INPUT + 2 = Device dependent (see Note 5)

MAX_AN_INPUT + 1 = Device dependent (see Note 5)

MAX_AN_INPUT = AN[MAX_AN_INPUT]

•

000001 = AN1

000000 = AN0

Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the

bit is cleared. Also, usage of the SAMP bit will cause settings of the SAMC<9:0> bits (ADCCON2<25:16>)

to be ignored.

2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC. All Class 1 analog

inputs are not affected by the SAMP bit.

3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit

and only after setting the RQCNVRT bit to start the analog-to-digital conversion.

4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits and

STRGSRC<4:0> bits should be set to ‘00000’ to disable all external hardware triggers and prevent them

from interfering with the software-controlled sampling command signal SAMP and with the

software-controlled trigger RQCNVRT.

5: Depending on the device, the function will vary. Refer to the “ADC” chapter in the specific device data

sheet to determine the function that is available for your device.

PIC32 Family Reference Manual

bit 10 STRGEN2: ADC2 Presynchronized Triggers bit

1 = ADC2 uses presynchronized triggers

0 = ADC2 does not use presynchronized triggers

bit 9 STRGEN1: ADC1 Presynchronized Triggers bit

1 = ADC1 uses presynchronized triggers

0 = ADC1 does not use presynchronized triggers

bit 8 STRGEN0: ADC0 Presynchronized Triggers bit

1 = ADC0 uses presynchronized triggers

0 = ADC0 does not use presynchronized triggers

bit 7 Unimplemented: Read as ‘ ’

bit 6 SSAMPEN6: ADC6 Synchronous Sampling bit

1 = ADC6 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC6 does not use synchronous sampling

bit 5 SSAMPEN5: ADC5 Synchronous Sampling bit

1 = ADC5 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC5 does not use synchronous sampling

bit 4 SSAMPEN4: ADC4 Synchronous Sampling bit

1 = ADC4 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC4 does not use synchronous sampling

bit 3 SSAMPEN3: ADC3 Synchronous Sampling bit

1 = ADC3 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC3 does not use synchronous sampling

bit 2 SSAMPEN2: ADC2Synchronous Sampling bit

1 = ADC2 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC2 does not use synchronous sampling

bit 1 SSAMPEN1: ADC1 Synchronous Sampling bit

1 = ADC1 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC1 does not use synchronous sampling

bit 0 SSAMPEN0: ADC0 Synchronous Sampling bit

1 = ADC0 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC0 does not use synchronous sampling

PIC32 Family Reference Manual

bit 20 SIGN10: AN10 Signed Data Mode bit

1 = AN10 is using Signed Data mode

0 = AN10 is using Unsigned Data mode

bit 19 DIFF9: AN9 Mode bit

1 = AN9 is using Differential mode

0 = AN9 is using Single-ended mode

bit 18 SIGN9: AN9 Signed Data Mode bit

1 = AN9 is using Signed Data mode

0 = AN9 is using Unsigned Data mode

bit 17 DIFF8: AN 8 Mode bit

1 = AN8 is using Differential mode

0 = AN8 is using Single-ended mode

bit 16 SIGN8: AN8 Signed Data Mode bit

1 = AN8 is using Signed Data mode

0 = AN8 is using Unsigned Data mode

bit 15 DIFF7: AN7 Mode bit

1 = AN7 is using Differential mode

0 = AN7 is using Single-ended mode

bit 14 SIGN7: AN7 Signed Data Mode bit

1 = AN7 is using Signed Data mode

0 = AN7 is using Unsigned Data mode

bit 13 DIFF6: AN6 Mode bit

1 = AN6 is using Differential mode

0 = AN6 is using Single-ended mode

bit 12 SIGN6: AN6 Signed Data Mode bit

1 = AN6 is using Signed Data mode

0 = AN6 is using Unsigned Data mode

bit 11 DIFF5: AN5 Mode bit

1 = AN5 is using Differential mode

0 = AN5 is using Single-ended mode

bit 10 SIGN5: AN5 Signed Data Mode bit

1 = AN5 is using Signed Data mode

0 = AN5 is using Unsigned Data mode

bit 9 DIFF4: AN4 Mode bit

1 = AN4 is using Differential mode

0 = AN4 is using Single-ended mode

bit 8 SIGN4: AN4 Signed Data Mode bit

1 = AN4 is using Signed Data mode

0 = AN4 is using Unsigned Data mode

bit 7 DIFF3: AN3 Mode bit

1 = AN3 is using Differential mode

0 = AN3 is using Single-ended mode

bit 6 SIGN3: AN3 Signed Data Mode bit

1 = AN3 is using Signed Data mode

0 = AN3 is using Unsigned Data mode

bit 5 DIFF2: AN2 Mode bit

1 = AN2 is using Differential mode

0 = AN2 is using Single-ended mode

PIC32 Family Reference Manual

Bit Range Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIFF31 SIGN31 DIFF30 SIGN30 DIFF29 SIGN29 DIFF28 SIGN28

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIFF27 SIGN27 DIFF26 SIGN26 DIFF25 SIGN25 DIFF24 SIGN24

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIFF23 SIGN23 DIFF22 SIGN22 DIFF21 SIGN21 DIFF20 SIGN20

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIFF19 SIGN19 DIFF18 SIGN18 DIFF17 SIGN17 DIFF16 SIGN16

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 DIFF31: AN31 Mode bit

1 = AN31 is using Differential mode

0 = AN31 is using Single-ended mode

bit 30 SIGN31: AN31 Signed Data Mode bit

1 = AN31 is using Signed Data mode

0 = AN31 is using Unsigned Data mode

bit 29 DIFF30: AN30 Mode bit

1 = AN30 is using Differential mode

0 = AN30 is using Single-ended mode

bit 28 SIGN30: AN30 Signed Data Mode bit

1 = AN30 is using Signed Data mode

0 = AN30 is using Unsigned Data mode

bit 27 DIFF29: AN29 Mode bit

1 = AN29 is using Differential mode

0 = AN29 is using Single-ended mode

bit 26 SIGN29: AN29 Signed Data Mode bit

1 = AN29 is using Signed Data mode

0 = AN29 is using Unsigned Data mode

bit 25 DIFF28: AN28 Mode bit

1 = AN28 is using Differential mode

0 = AN28 is using Single-ended mode

bit 24 SIGN28: AN28 Signed Data Mode bit

1 = AN28 is using Signed Data mode

0 = AN28 is using Unsigned Data mode

bit 23 DIFF27: AN27 Mode bit

1 = AN27 is using Differential mode

0 = AN27 is using Single-ended mode

bit 22 SIGN27: AN27 Signed Data Mode bit

1 = AN27 is using Signed Data mode

0 = AN27 is using Unsigned Data mode

bit 21 DIFF26: AN26 Mode bit

1 = AN26 is using Differential mode

0 = AN26 is using Single-ended mode

PIC32 Family Reference Manual

bit 4 SIGN18: AN18 Signed Data Mode bit

1 = AN18 is using Signed Data mode

0 = AN18 is using Unsigned Data mode

bit 3 DIFF17: AN17 Mode bit

1 = AN17 is using Differential mode

0 = AN17 is using Single-ended mode

bit 2 SIGN17: AN17 Signed Data Mode bit

1 = AN17 is using Signed Data mode

0 = AN17 is using Unsigned Data mode

bit 1 DIFF16: AN16 Mode bit

1 = AN16 is using Differential mode

0 = AN16 is using Single-ended mode

bit 0 SIGN16: AN16 Signed Data Mode bit

1 = AN16 is using Signed Data mode

0 = AN16 is using Unsigned Data mode

Section 22. 12-bit High-Speed SAR ADC

Bit Range Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIFF47 SIGN47 DIFF46 SIGN46 DIFF45 SIGN45 DIFF44 SIGN44

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIFF43 SIGN43 DIFF42 SIGN42 DIFF41 SIGN41 DIFF40 SIGN40

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIFF39 SIGN39 DIFF38 SIGN38 DIFF37 SIGN37 DIFF36 SIGN36

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DIFF35 SIGN35 DIFF34 SIGN34 DIFF33 SIGN33 DIFF32 SIGN32

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 DIFF47: AN47 Mode bit

1 = AN47 is using Differential mode

0 = AN47 is using Single-ended mode

bit 30 SIGN47: AN47 Signed Data Mode bit

1 = AN47 is using Signed Data mode

0 = AN47 is using Unsigned Data mode

bit 29 DIFF46: AN46 Mode bit

1 = AN46 is using Differential mode

0 = AN46 is using Single-ended mode

bit 28 SIGN46: AN46 Signed Data Mode bit

1 = AN46 is using Signed Data mode

0 = AN46 is using Unsigned Data mode

bit 27 DIFF45: AN45 Mode bit

1 = AN45 is using Differential mode

0 = AN45 is using Single-ended mode

bit 26 SIGN45: AN45 Signed Data Mode bit

1 = AN45 is using Signed Data mode

0 = AN45 is using Unsigned Data mode

bit 25 DIFF44: AN44 Mode bit

1 = AN44 is using Differential mode

0 = AN44 is using Single-ended mode

bit 24 SIGN44: AN44 Signed Data Mode bit

1 = AN44 is using Signed Data mode

0 = AN44 is using Unsigned Data mode

bit 23 DIFF43: AN43 Mode bit

1 = AN43 is using Differential mode

0 = AN43 is using Single-ended mode

bit 22 SIGN43: AN43 Signed Data Mode bit

1 = AN43 is using Signed Data mode

0 = AN43 is using Unsigned Data mode

bit 21 DIFF42: AN42 Mode bit

1 = AN42 is using Differential mode

0 = AN42 is using Single-ended mode

Section 22. 12-bit High-Speed SAR ADC

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TRGSRC3<4:0>

23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TRGSRC2<4:0>

15:8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TRGSRC1<4:0>

7:0

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TRGSRC0<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-24 TRGSRC3<4:0>: Trigger Source for Conversion of Analog Input AN3 Select bits

11111 00100 - = Refer to the “ADC” chapter in the specific device data sheet for trigger source selections

00011 = Scan Trigger (STRIG)

00010 = Global level software trigger (GLSWTRG)

00001 = Global software edge Trigger (GSWTRG)

00000 = No Trigger

For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits

(ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSSx bits to be set in the

ADCCSSx registers.

bit 23-21 Unimplemented: Read as ‘0’

bit 20-16 TRGSRC2<4:0>: Trigger Source for Conversion of Analog Input AN2 Select bits

See bits 28-24 for bit value definitions.

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 TRGSRC1<4:0>: Trigger Source for Conversion of Analog Input AN1 Select bits

See bits 28-24 for bit value definitions.

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 TRGSRC0<4:0>: Trigger Source for Conversion of Analog Input AN0 Select bits

See bits 28-24 for bit value definitions.

Section 22. 12-bit High-Speed SAR ADC

Bit Range Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

— — — AINID<4:0>

7:0

R/W-0 R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ENDCMP DCMPGIEN DCMPED IEBTWN IEHIHI IEHILO IELOHI IELOLO

Legend: HS = Hardware Set HC = Hardware Cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as ‘0’

bit 12-8 AINID<4:0>: Digital Comparator ‘x’ Analog Input Identification (ID) bits

When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being

monitored by the Digital Comparator.

Note: Only analog inputs <31:0> can be processed by the Digital Comparator module ‘x’ (‘x’ = 2-6).

11111 = AN31 is being monitored

11110 = AN30 is being monitored

•

00001 = AN1 is being monitored

00000 = AN0 is being monitored

bit 7 ENDCMP: Digital Comparator ‘x’ Enable bit

1 = Digital Comparator ‘x’ is enabled

0 = Digital Comparator ‘x’ is not enabled, and the DCMPED status bit (ADCCMPCONx<5>) is cleared

bit 6 DCMPGIEN: Digital Comparator ‘x’ Interrupt Enable bit

1 = A Digital Comparator ‘x’ interrupt is generated when the DCMPED status bit (ADCCMPCONx<5>) is

set

0 = A Digital Comparator ‘x’ interrupt is disabled

bit 5 DCMPED: Digital Comparator ‘x’ “Output True” Event Status bit

The logical conditions under which the digital comparator gets “True” are defined by the IEBTWN, IEHIHI,

IEHILO, IELOHI and IELOLO bits.

Note: This bit is cleared by reading the AINID<5:0> bits (ADCCMPCON1<13:8>) or by disabling the

Digital Comparator module (by setting ENDCMP to ‘0’).

1 = Digital Comparator ‘x’ output true event has occurred (output of Comparator is ‘1’)

0 = Digital Comparator ‘x’ output is false (output of Comparator is ‘0’)

bit 4 IEBTWN: Between Low/High Digital Comparator ‘x’ Event bit

1 = Generate a digital comparator event when the DCMPLO<15:0> bits DATA<31:0> bits

DCMPHI<15:0> bits

0 = Do not generate a digital comparator event

bit 3 IEHIHI: High/High Digital Comparator ‘x’ Event bit

1 = Generate a Digital Comparator ‘x’ Event when the DCMPHI<15:0> bits  DATA<31:0> bits

0 = Do not generate an event

bit 2 IEHILO: High/Low Digital Comparator ‘x’ Event bit

1 = Generate a Digital Comparator ‘x’ Event when the DATA<31:0> bits

DCMPHI<15:0> bits

0 = Do not generate an event

Section 22. 12-bit High-Speed SAR ADC

Bit Range Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA<31:24>

23:16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA<23:16>

15:8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA<15:8>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DATA<31:0>: ADC Converted Data Output bits.

Note 1: When an alternate input is used as the input source for a dedicated ADC module, the data output is still

read from the Primary input Data Output Register.

2: Reading the ADCDATAx register value after changing the FRACT bit converts the data into the format

specified by FRACT bit.

Section 22. 12-bit High-Speed SAR ADC

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

EIRDY31 EIRDY30 EIRDY29 EIRDY28 EIRDY27 EIRDY26 EIRDY25 EIRDY24

23:16

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

EIRDY23 EIRDY22 EIRDY21 EIRDY20 EIRDY19 EIRDY18 EIRDY17 EIRDY16

15:8

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

EIRDY15 EIRDY14 EIRDY13 EIRDY12 EIRDY11 EIRDY10 EIRDY9 EIRDY8

7:0

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

EIRDY7 EIRDY6 EIRDY5 EIRDY4 EIRDY3 EIRDY2 EIRDY1 EIRDY0

Legend: HS = Hardware Set HC = Hardware Cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 EIRDY31:EIRDY0: Early Interrupt for Corresponding Analog Input Ready bits

1 = This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be

generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs, this

bit will set as per the configuration of the ADCEIS<2:0> bits in the ADCxTIME register. For the shared

ADC module, this bit will be set as per the configuration of the ADCEIS<2:0> bits in the ADCCON2

0 = Interrupts are disabled

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

EIRDY63 EIRDY62 EIRDY61 EIRDY60 EIRDY59 EIRDY58 EIRDY57 EIRDY56

23:16

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

EIRDY55 EIRDY54 EIRDY53 EIRDY52 EIRDY51 EIRDY50 EIRDY49 EIRDY48

15:8

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

EIRDY47 EIRDY46 EIRDY45 EIRDY44 EIRDY43 EIRDY42 EIRDY41 EIRDY40

7:0

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

EIRDY39 EIRDY38 EIRDY37 EIRDY36 EIRDY35 EIRDY34 EIRDY33 EIRDY32

Legend: HS = Hardware Set HC = Hardware Cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 EIRDY63:EIRDY32: Early Interrupt for Corresponding Analog Input Ready bits

1 = This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be

generated if early interrupts are enabled in the ADCEIEN2 register. For the Class 1 analog inputs, this

bit will set as per the configuration of the ADCEIS<2:0> bits in the ADCxTIME register. For the shared

ADC module, this bit will be set as per the configuration of the ADCEIS<2:0> bits in the ADCCON2

0 = Interrupts are disabled

PIC32 Family Reference Manual

Bit Range Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

AN<31:23>

23:16

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

AN<23:16>

15:8

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

AN<15:8>

7:0

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

AN<7:0>

Legend: HS = Hardware Set HC = Hardware Cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 AN<31:0>: ADC Analog Input bits

These bits reflect the system configuration and are updated during boot-up time. By reading these

read-only bits, the user application can determine whether or not an analog input in the device is available.

AN<31:0>: Reflects the presence or absence of the respective analog input (AN31-AN0).

Bit Range Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

AN<63:56>

23:16

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

AN<55:48>

15:8

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

AN<47:40>

7:0

R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC

AN<39:32>

Legend: HS = Hardware Set HC = Hardware Cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 AN<63:32>: ADC Analog Input bits

These bits reflect the system configuration and are updated during boot-up time. By reading these

read-only bits, the user application can determine whether or not an analog input in the device is available.

AN<63:32>: Reflects the presence or absence of the respective analog input (AN63-AN32).

Section 22. 12-bit High-Speed SAR ADC

22.4 ADC MODULE CONFIGURATION

Operation of the ADC module is directed through bit settings in the specific registers. The

following instructions summarize the actions and the settings. The options and details for each

configuration step are provided in the subsequent sections.

To configure the ADC module, perform the following steps:

1. Configure the analog port pins, as described in 22.4.1 “Configuring the Analog Port

Pins”.

2. Initialize the ADC calibration values by copying them from the factory-programmed

DEVADCx Flash registers into the corresponding ADCxCFG registers.

3. Select the analog inputs to the ADC multiplexers, as described in 22.4.2 “Selecting the

ADC Multiplexer Analog Inputs”.

4. Select the format of the ADC result, as described in 22.4.3 “Selecting the Format of the

ADC Result”.

5. Select the conversion trigger source, as described in 22.4.4 “Selecting the Conversion

Trigger Source”.

6. Select the voltage reference source, as described in 22.4.5 “Selecting the Voltage

Reference Source”.

7. Select the scanned inputs, as described in 22.4.6 “Selecting the Scanned Inputs”.

8. Select the analog-to-digital conversion clock source and prescaler, as described in

22.4.7 “Selecting the Analog-to-Digital Conversion Clock Source and Prescaler”.

9. Specify any additional acquisition time, if required, as described in 22.10 “ADC Sampling

Requirements”.

10. Turn on the ADC module, as described in Equation 22-2: “Sample Time for the Shared

ADC Module”.

11. Poll (or wait for the interrupt) for the voltage reference to be ready, as described in

22.4.5 “Selecting the Voltage Reference Source”.

12. Enable the analog and bias circuit for required ADC modules and after the ADC module

wakes-up, enable the digital circuit, as described in 22.7.3 “ADC Low-power Mode”

13. Configure the ADC interrupts (if required), as described in 22.6 “Interrupts”.

22.4.1 Configuring the Analog Port Pins

The ANSELx registers for the I/O ports associated with the analog inputs are used to configure

the corresponding pin as an analog or a digital pin. A pin is configured as analog input when the

corresponding ANSELx bit = 1. When the ANSELx bit = 0, the pin is set to digital control. The

ANSELx registers are set when the device comes out of Reset, causing the ADC input pins to be

configured as analog inputs by default.

The TRISx registers control the digital function of the port pins. The port pins that are required

as analog inputs must have their corresponding bit set in the specific TRISx register, configuring

the pin as an input. If the I/O pin associated with an ADC input is configured as an output by

clearing the TRISx bit, the port’s digital output level (V

or V

) will be converted. After a device

Reset, all of the TRISx bits are set. For more information on port pin configuration, refer to the

“I/O Ports” chapter of the specific device data sheet.

Note: When reading a PORT register that shares pins with the ADC, any pin configured

as an analog input reads as a ‘0’ when the PORT latch is read. Analog levels on any

pin that is defined as a digital input but not configured as an analog input, may cause

the input buffer to consume current that exceeds the device specification.

Section 22. 12-bit High-Speed SAR ADC

Example 22-1: Initializing and Using ADC Class 1 Input (Continued)

/* Configure ADCFLTRx */

ADCFLTR1 = 0; // No oversampling filters are used.

ADCFLTR2 = 0;

ADCFLTR3 = 0;

ADCFLTR4 = 0;

ADCFLTR5 = 0;

ADCFLTR6 = 0;

/* Set up the trigger sources */

ADCTRGSNSbits.LVL0 = 0; // Edge trigger

ADCTRGSNSbits.LVL1 = 0; // Edge trigger

ADCTRGSNSbits.LVL2 = 0; // Edge trigger

ADCTRG1bits.TRGSRC0 = 1; // Set AN0 to trigger from software.

ADCTRG1bits.TRGSRC1 = 1; // Set AN1 to trigger from software.

ADCTRG1bits.TRGSRC2 = 1; // Set AN2 to trigger from software.

/* Early interrupt */

ADCEIEN1 = 0; // No early interrupt

ADCEIEN2 = 0;

/* Turn the ADC on */

ADCCON1bits.ON = 1;

/* Wait for voltage reference to be stable */

while(!ADCCON2bits.BGVRRDY); // Wait until the reference voltage is ready

while(ADCCON2bits.REFFLT); // Wait if there is a fault with the reference voltage

/* Enable clock to analog circuit */

ADCANCONbits.ANEN0 = 1; // Enable the clock to analog bias

ADCANCONbits.ANEN1 = 1; // Enable the clock to analog bias

ADCANCONbits.ANEN2 = 1; // Enable the clock to analog bias

/* Wait for ADC to be ready */

while(!ADCANCONbits.WKRDY0); // Wait until ADC0 is ready

while(!ADCANCONbits.WKRDY1); // Wait until ADC1 is ready

while(!ADCANCONbits.WKRDY2); // Wait until ADC2 is ready

/* Enable the ADC module */

ADCCON3bits.DIGEN0 = 1; // Enable ADC0

ADCCON3bits.DIGEN1 = 1; // Enable ADC1

ADCCON3bits.DIGEN2 = 1; // Enable ADC2

while (1) {

/* Trigger a conversion */

ADCCON3bits.GSWTRG = 1;

/* Wait the conversions to complete */

while (ADCDSTAT1bits.ARDY0 == 0);

/* fetch the result */

result[0] = ADCDATA0;

while (ADCDSTAT1bits.ARDY1 == 0);

/* fetch the result */

result[1] = ADCDATA1;

while (ADCDSTAT1bits.ARDY2 == 0);

/* fetch the result */

result[2] = ADCDATA2;

* Process results here

* Note: Loop time determines the sampling time since all inputs are Class 1.

* If the loop time is small and the next trigger happens before the completion

* of set sample time, the conversion will happen only after the sample time

* has elapsed.

}

return (1);

}

Section 22. 12-bit High-Speed SAR ADC

22.4.3 Selecting the Format of the ADC Result

The data in the ADC Result register can be read in any of the four supported data formats. The

user can select from unsigned integer, signed integer, unsigned fractional, or signed fractional.

Integer data is right-justified and fractional data is left-justified.

• The integer or fractional data format selection is specified globally for all analog inputs

using the Fractional Data Output Format bit, FRACT (ADCCON1<23>)

• The signed or unsigned data format selection can be independently specified for each

individual analog input using the SIGNx bits in the ADCIMCONx registers.

Table 22-4 provides how ADC result is formatted.

Table 22-4: ADC Result Format Results

FRACT SIGNx Description 32-bit Output Data Format

0 0 Unsigned integer

0000 0000 0000 0000

0000 dddd dddd dddd

0 1 Signed integer

ssss ssss ssss ssss

ssss sddd dddd dddd

1 0 Fractional

dddd dddd dddd 0000

0000 0000 0000 0000

1 1 Signed fractional

sddd dddd dddd dddd

0000 0000 0000 0000

PIC32 Family Reference Manual

Figure 22-9: Presynchronized Trigger (STRGEN bit) and Synchronized Sampling (SSAMPEN bit)

Control Clock (TQ)

Trigger (1 period jitter)

Presynchronized Trigger

Sample

ends

‘00’: STRGENx = 0, SSAMPENx = 0

W6$0&[

ADCxTIME<9:0>

2 * TQ

‘10’: STRGENx = 1, SSAMPENx = 0

Sample ends,

Conversion starts

tSAMCx already completed in past

Conversion

starts

7RWDO6DPSOH7LPH Sample ends,

Conversion starts

µ[¶675*(1[  RU 66$03(1[   

Section 22. 12-bit High-Speed SAR ADC

Figure 22-12: Presynchronized Trigger Waveform (When multiple Class 1 inputs are used to convert phase

currents of a 3-phase motor)

Since the trigger and synchronization works with the control clock (T

) and the ADC modules

work on their own clock (T

), proper synchronization should be maintained between the two

clock domains. For proper synchronization, two bits are provided, FSSCLKEN (ADCCON1<10>

and FSPBCLKEN (ADCCON1<9>). The usage of these bits are as follows:

• Set the FSSCLKEN bit if one of the following conditions is true:

- ADCSEL<1:0> = (SYSCLK)

- ADCSEL<1:0> = (REFCLK3) and the REFCLK3 is also a divided clock derived from

the system clock (SYSCLK)

- ADCSEL<1:0> = (FRC) and the system clock is also set to be driven by FRC

- ADCSEL<1:0> = PBCLK (for PIC32MZ family)/SYSCLK (for PIC32MK family) and the

PBCLK (for PIC32MZ family) clock is a divided clock derived from the system clock

• Set the FSPBCLKEN bit if one of the following conditions is true:

- ADCSEL<1:0> = SYSCLK and the peripheral clock is a divided clock from the system

clock and the ADC is not faster than the peripheral clock. This means that both the

peripheral clock and the ADC clock are divided from the same system clock, but the

division ratio of the ADC clock is higher than or equal to the division ratio of the periph-

eral clock, which makes the peripheral clock synchronous to, but not slower than the

ADC clock.

- ADCSEL<1:0> = REFCLK3 and REFCLK3 is synchronous to, and slower than the

peripheral clock, which is true if the peripheral clock is also derived from the

REFCLK3, but is not slower than the ADC clock

- ADCSEL<1:0> = FRC and the peripheral clock is also divided from the FRC and is not

slower than the ADC clock

- ADCSEL<1:0> = PBCLK (for PIC32MZ family/SYSCLK (for PIC32MK family)

Control Clock (TQ)

Trigger (1 period jitter)

Although ADC1, ADC2, and ADC3 use the common

trigger, due to propagation delay, the “end of sampling

and start of conversion” does not occur at the exact

same time.

‘00’: STRGEN0 0=0, SSAMPEN = 0

‘00’: STRGEN1 1=0, SSAMPEN = 0

‘00’: STRGEN2 2=0, SSAMPEN = 0

ADC0

ADC1

ADC2

PIC32 Family Reference Manual

Example 22-3: ADC Scanning Multiple Inputs (Continued)

/* Set up the trigger sources */

ADCTRG1bits.TRGSRC0 = 3; // Set AN0 (Class 1) to trigger from scan source

ADCTRG3bits.TRGSRC8 = 3; // Set AN8 (Class 2) to trigger from scan source

// AN40 (Class 3) always uses scan trigger source

/* Early interrupt */

ADCEIEN1 = 0; // No early interrupt

ADCEIEN2 = 0;

/* Turn the ADC on */

ADCCON1bits.ON = 1;

/* Wait for voltage reference to be stable */

while(!ADCCON2bits.BGVRRDY); // Wait until the reference voltage is ready

while(ADCCON2bits.REFFLT); // Wait if there is a fault with the reference voltage

/* Enable clock to analog circuit */

ADCANCONbits.ANEN0 = 1; // Enable the clock to analog bias ADC0

ADCANCONbits.ANEN7 = 1; // Enable, ADC7

/* Wait for ADC to be ready */

while(!ADCANCONbits.WKRDY0); // Wait until ADC0 is ready

while(!ADCANCONbits.WKRDY7); // Wait until ADC7 is ready

/* Enable the ADC module */

ADCCON3bits.DIGEN0 = 1; // Enable ADC0

ADCCON3bits.DIGEN7 = 1; // Enable ADC7

while (1) {

/* Trigger a conversion */

ADCCON3bits.GSWTRG = 1;

/* Wait the conversions to complete */

while (ADCDSTAT1bits.ARDY0 == 0);

/* fetch the result */

result[0] = ADCDATA0;

while (ADCDSTAT1bits.ARDY8 == 0);

/* fetch the result */

result[1] = ADCDATA8;

while (ADCDSTAT2bits.ARDY40 == 0);

/* fetch the result */

result[2] = ADCDATA40;

* Process results here

}

return (1);

}

Section 22. 12-bit High-Speed SAR ADC

Figure 22-17: 4x Oversampling of a Class 2 Input

Example 22-5: ADC Digital Oversampling Filter

Sample AN8 Hold AN8

Convert AN8

Prior to trigger, S&H is

disconnected

Initial trigger clears the

accumulator and starts

the sampling process

Sample AN8 Hold AN8

Convert AN8

Sample AN8 Hold AN8

Convert AN8

Sample AN8 Hold AN8

Convert AN8

Converted results are added to the accumulator

Sample time decided by the SAMC<9:0> bits

(AD CON2<25:16>)&

Last conversion results in a 14-bit sum, the sum is right-shifted by one

producing a 13-bit result in FLTRDATA<15:0> (AD&FLTR <15:0>)[

Retriggers are generated automatically, until the number of samples

set by OVRSAM<2:0> (AD&FLTRx<28:26>) are captured.

Disconnected

int main(int argc, char** argv) {

int result;

/* Configure ADCCON1 */

ADCCON1 = 0; // No ADCCON1 features are enabled including: Stop-in-Idle, turbo,

// CVD mode, Fractional mode and scan trigger source.

/* Configure ADCCON2 */

ADCCON2 = 0; // Since, we are using only the Class 1 inputs, no setting is

// required for ADCDIV

/* Initialize warm up time register */

ADCANCON = 0;

ADCANCONbits.WKUPCLKCNT = 5; // Wake-up exponent = 32 * TADx

/* Clock setting */

ADCCON3 = 0;

ADCCON3bits.ADCSEL = 0; // Select input clock source

ADCCON3bits.CONCLKDIV = 1; // Control clock frequency is half of input clock

ADCCON3bits.VREFSEL = 0; // Select AVDD and AVSS as reference source

ADC0TIMEbits.ADCDIV = 1; // ADC0 clock frequency is half of control clock = TAD0

ADC0TIMEbits.SAMC = 5; // ADC0 sampling time = 5 * TAD0

ADC0TIMEbits.SELRES = 3; // ADC0 resolution is 12 bits

/* Select analog input for ADC modules, no presync trigger, not sync sampling */

ADCTRGMODEbits.SH0ALT = 0; // ADC0 = AN0

/* Select ADC input mode */

ADCIMCON1bits.SIGN0 = 0; // unsigned data format

ADCIMCON1bits.DIFF0 = 0; // Single ended mode

/* Configure ADCGIRQENx */

ADCGIRQEN1 = 0; // No interrupts are used

ADCGIRQEN2 = 0;

/* Configure ADCCSSx */

ADCCSS1 = 0; // No scanning is used

ADCCSS2 = 0;

Section 22. 12-bit High-Speed SAR ADC

Example 22-6: ADC FIFO Usage for Class 1 Input (Continued)

/* Configure ADCFLTRx */

ADCFLTR1 = 0; // Clear all bits

ADCFLTR2 = 0;

ADCFLTR3 = 0;

ADCFLTR4 = 0;

ADCFLTR5 = 0;

ADCFLTR6 = 0;

/* Set up the trigger sources */

ADCTGSNSbits.LVL0 = 0; // Edge trigger

ADCTRG0bits.TRGSRC0 = 1; // Set AN0 to trigger from software.

/* Early interrupt */

ADCEIEN1 = 0; // No early interrupt

ADCEIEN2 = 0;

/* Set FIFO */

ADCFSTAT = 0; // Clear all bits

ADCFSATbits.ADC0EN = 1; // Select ADC0

ADCFSATbits.FEN = 1; // Enable FIFO

/* Turn the ADC on */

ADCCON1bits.ON = 1;

/* Wait for voltage reference to be stable */

while(!ADCCON2bits.BGVRRDY); // Wait until the reference voltage is ready

while(ADCCON2bits.REFFLT); // Wait if there is a fault with the reference voltage

/* Enable clock to analog circuit */

ADCANCONbits.ANEN0 = 1; // Enable the clock to analog bias and digital control

/* Wait for ADC to be ready */

while(!ADCANCONbits.WKRDY0); // Wait until ADC0 is ready

/* Enable the ADC module */

ADCCON3bits.DIGEN0 = 1; // Enable ADC0

while (1) {

/* Trigger a conversion */

ADCCON3bits.GSWTRG = 1;

/* Wait the conversions to complete and data available in FIFO */

while (ADCFSTATbits.FRDY == 0);

/* Once FIFO bit is set, read all possible data, until bit is clear */

while(ADCFSTATbits.FRDY)

{

/* If data overflow occurred in FIFO, break read process */

if(ADCFSTATbits.FWROVERR)

{

break;

}

/* if ADC ID is really '0', read data.

This is more appropriate when multiple ADC modules are

using the FIFO, therefore, reading the ADC ID will

identify the ADC and data relation */

if(ADCFSTATbits.ADCID == 0)

{

/* Read data from FIFO */

result[index] = ADCFIFO;

/* For each FIFO read, ADCFSTATbits.FCNT will keep reducing */

index++;

if(index >= 128)

index = 0;

}

* Process results here

}

return (1);

}

Section 22. 12-bit High-Speed SAR ADC

The CVD module internally calculates the difference between V

P and V

and stores the data

in the CVDDATA<15:0> bits (ADCCMPCON1<31:16>) in signed format. The plot in Figure 22-23

shows how during a touch event, the increase in external capacitance causes the (V

- V

to be higher than the non-touch condition (decreased external capacitance).

Figure 22-23: CVD Signal - Difference Between Pressed and Released Differential Values

Equation 22-3 shows the relation (V

P - V

N).

Equation 22-3: V

P and V

N Relation

During a touch condition, C

EXT

increases and (V

P - V

N) increases.

During no touch condition, C

EXT

decreases and (V

P - V

N) reduces.

Digital Comparator 1 is linked to CVD and it can be used to generate a comparator event and

interrupt when a touch is detected, by setting the IEHIHI bit (ADCCMPCON1<3>). The digital

comparator can generate an event when measured (V

P - V

N) is above the value set in the

DCMPHI<15:0> bit (ADCCMP1<31:16>). When the comparator event is detected by reading the

DCMPED bit (ADCCMPCON1<5>), or inside the ISR, the analog input that caused the touch

event can be read from the AINID<5:0> bits (ADCCMPCON1<13:8>).

To ensure maximum sensitivity, C

INT

should have similar value as C

PAD

, which can be done by

suitably selecting the value of C

PLINE

capacitance through the CVDCPL<2:0> bits

(ADCCON2<28:26>).

Time

Negative Phase Positive Phase

Precharge Acquisition Conversion Precharge Acquisition Conversion

Voltage

Internal ADC Hold Capacitor

External Capacitive Sensor

Vreleased

Vpressed

Note: Before CVD is enabled by setting the CVDEN bit, external triggers for all Class 2

and Class 3 inputs are disabled by clearing the TRGSRC<4:0> and

STRGSRC<4:0> bits.

P V

N–  V

EXT

IN T

– 

EXT

IN T

+ 

------------------------------------

 

 

=

Produktspecifikationer

Varumärke:	Microchip
Kategori:	Inte kategoriserad
Modell:	PIC32MZ2025DAS169

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