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SY87729L
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SY87729L
3.3V AnyClock®, 10MHz to 365MHz
Fractional N Synthesizer
AnyClock and AnyRate are registered trademarks of Micrel, Inc.
MicroWire is a trademark of National Semiconductor
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
General Description
The SY87729L is a complete rate independent frequency
synthesizer integrated circuit. From a single reference
source, this device generates a differential PECL
reference frequency for Micrel's SY87721L 10Mbps to
2.7Gbps combined CDR and CMU.
The SY87729L generates an exactly correct reference
frequency for common data transport protocols. This is
especially important in transponder applications, where a
standards compliant protocol data unit must be generated
downstream, even in the absence of any signal from the
associated upstream interface.
In addition, SY87729L will generate exactly correct
reference frequencies for common data transport protocols
augmented by forward error correction codes.
For proprietary applications, the SY87729L generates
reference frequencies guaranteed to enable the SY87721L
CDR to lock to any possible baud rate in its range.
SY87729L accepts configuration via a MicroWire™
interface.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
AnyClock®
Features
• Fractional synthesizer from 10MHz to 365MHz from a
single 27MHz reference oscillator
• Generates exactly the correct frequency for common
transport protocols with or without FEC
• Directly enables SY87721L to lock onto any data rate
within its range
• Exceeds BellCore and ITU jitter generation
specifications
• Programmable via MicroWire™ interface
• Available in 32-Pin EPAD-TQFP package
Applications
• Metro access system
• Transponders
• Multiplexers: access, add drop mux
• SONET/SDH/ATM-based transmission systems,
modules and test equipment
• Broadband cross-connects
• Fiber optic test equipment
• Protocols supported:
− OC-1, OC-3, OC-12, OC-48, ATM, Gigabit Ethernet,
Fast Ethernet, Fibre Channel, 2X Fibre Channel,
1394, InfiniBand, Proprietary Optical Transport
July 2011 M9999-072111-G
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc. SY87729L
July 2011 2 M9999-072111-G
hbwhelp@micrel.com
Ordering Information(1)
Part Number Package Type Operating Range Package Marking
SY87729LHY(3, 3) H32-2 Industrial SY87729LHY with
Pb-Free Bar-Line Indicator
SY87729LHYTR(2, 3) H32-2 Industrial SY87729LHY with
Pb-Free Bar-Line Indicator
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-free package is recommended for new designs.
System Block Diagram
or (408) 955-1690
Micrel, Inc. SY87729L
July 2011 3 M9999-072111-G
hbwhelp@micrel.com
Functional Block Diagram
or (408) 955-1690
Micrel, Inc. SY87729L
July 2011 4 M9999-072111-G
hbwhelp@micrel.com
Pin Configuration
32-Pin ePad TQFP (H32-2)
Pin Description
Pin Number Pin Name Pin Function
1, 24 VCCA Analog Supply Voltage.
2, 5,11, 12, 13,
15, 16, 19, 20,
23, 28, 29
NC No Connection. These pins are to be left unconnected.
3, 4 REFCLK± Differential PECL Input. .
6 PROGCS
Program Interface Chip Select (TTL Input). This signal forms part of the MicroWire™ interface.
When active high, this signal permits the acquisition of serial data. A falling edge on this input
causes SY87729L to re-acquire lock to a new frequency, based on the program downloaded to it.
7 PROGDI Program Interface Data In (TTL Input). One data bit is sampled on each rising edge of PRGSK,
while PROGCS is active high.
8 PROGSK Program Interface Serial Clock (TTL Input). One bit of configuration data is read in each clock
cycle
9, 17 VCC Supply Voltage.
10 GND Ground.
14 LOCKED
Lock Output. This indicates proper operation of all the blocks in the clock synthesis chain. Logic
high indicates that SY87729L is generating the expected frequency at the CLKOUT± output.
Logic low indicates that one or more PLL in the clock synthesis chain has yet to achieve proper
lock.
18 VCCO Output Supply Voltage.
21, 22 CLKOUT± Reference Clock Output. This is the synthesized clock generated from REFCLK±. It can be used
to supply a reference clock to a data recovery device, such as Micrel’s SY87721L.
25, 32 GNDA Analog Ground.
26, 27 WRVCF±
Wrapper Filter (Analog I/O). These pins connect to the output from the wrapper synthesizer
charge pump, as well as the input to the corresponding VCO. A filter network, as described
below, converts the charge pump current to a voltage, and adjusts loop bandwidth
30, 31 FNVCF±
Fractional-N Filter (Analog I/O). These pins connect to the output from the fractional-N
synthesizer charge pump, as well as the input to the corresponding Voltage Controlled Oscillator
(VCO). A filter network, as described below, converts the charge pump current to a voltage, and
adjusts loop bandwidth
or (408) 955-1690
Micrel, Inc. SY87729L
July 2011 5 M9999-072111-G
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(1)
Supply Voltage (VCC).................................... –0.5V to +4.0V
Input Voltage (VIN). ....................................–0.5V to VCC
ECL Output Current (IOUT)
Continuous............................................................50mA
Surge ..................................................................100mA
Lead Temperature (soldering, 20sec.)....................... 260°C
Storage Temperature (Ts) .........................–65°C to +150°C
Operating Ratings(2)
Supply Voltage (VCC)...........................................+3.3V ±5%
Ambient Temperature (TA
) ..........................–40°C to +85°C
Junction Temperature (TA) ........................................ 125°C
Package Thermal Resistance
ePad TQFP (θJA)(3)
Still-Air......................................................27.6°C/W
500lfpm ....................................................20.7°C/W
DC Electrical Characteristics
VCC = VCCO = VCCA= 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power Supply Voltage 3.15 3.3 3.45 V
ICC Power Supply Current No output load. − 205 275 mA
PECL DC Electrical Characteristics
VCC = VCCO = VCCA= 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C.
Symbol Parameter Condition Min. Typ. Max. Units
VIH
Input HIGH Voltage VCC − 1.165 − VCC − 0.880 V
VIL Input LOW Voltage VCC − 1.810 − VCC − 1.475 V
VOH Output HIGH Voltage 50Ω to VCC −2V VCC − 1.075 − VCC − 0.830 V
VOL Output LOW Voltage 50Ω to VCC −2V VCC − 1.860 − VCC − 1.570 V
IIL Input LOW Current(4, 5) VIN = VIL(MIN) − − −1.5 µA
TTL DC Electrical Characteristics
VCC = VCCO = VCCA= 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C.
Symbol Parameter Condition Min. Typ. Max. Units
VIH
Input HIGH Voltage 2.0 − − V
VIL Input LOW Voltage − − 0.8 V
VOH Output HIGH Voltage IOH = −2mA 2.0 − − V
VOL Output LOW Voltage I
OL = 4mA − − 0.5 V
VIN = 2.7V, VCC = MAX − − + 20
IIH
Input HIGH Current VIN = VCC, VCC = MAX − − + 100 µA
IIL Input LOW Current(4, 5) VIN = 0.5V, VCC = MAX − − − 300 µA
IOS Output Short-Circuit Current VOUT = 0V (1sec. MAX) − − −100 250 mA
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Measured with die attach pad soldered to PCB, JEDEC-standard multi-layer board.
4. The REFCLK+ pin has a nominal 75Ω pull-down resistor connected to ground.
5. The REFCLK− pin has a nominal 75 pull-up resistor connected to VΩ pull-down resistor connected to ground and a nominal has a nominal 75ΩCC.
Micrel, Inc. SY87729L
July 2011 6 M9999-072111-G
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCC = VCCO = VCCA= 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C.
Symbol Parameter Condition Min. Typ. Max. Units
tIRF REFCLK Input Rise/Fall Times − − 2.0 ns
tREFPWH REFCLK Pulse Width HIGH 5 − − ns
tREFPWL REFCLK Pulse Width LOW 5 − − ns
tCSSK PROGCS-to-PROGSK Preset 100 − − ns
tSKCS PROGSK-to-PROGCS Recovery 100 − − ns
tSKP PROGSK Period 200 − − ns
tSKPWH PROGSK Pulse Width HIGH 70 − − ns
tSKPWL PROGSK Pulse Width LOW 70 − − ns
tDIS PROGDI Data Setup 20 − − ns
tDIH
PROGDI Data Hold 20 − − ns
CLKOUT Duty Cycle tCLKPWH/(tCLKPWH + tCLKPWL) 25 − 75 % of UI
CLKOUT Maximum Frequency 365 − − MHz
Acquisition Lock Time 27MHz Reference Clock − − 0.1 sec.
Fractional-N VCO Operating Range 540 − 729 MHz
Wrapper VCO Operating Range 540 − 729 MHz
Micrel, Inc. SY87729L
July 2011 7 M9999-072111-G
hbwhelp@micrel.com
Timing Waveforms
or (408) 955-1690
Micrel, Inc. SY87729L
July 2011 9 M9999-072111-G
hbwhelp@micrel.com
Whereas P sets the integer part of the multiplication
factor from input to output frequency, the control circuit
determines the fractional part. By mixing the output of
the P and P-1 dividers correctly, the control circuit can
fashion any output frequency from P-1 times the input to
P times the input, as long as that ratio can be expressed
as a ratio of integers.
Figure 2. 11/3 Example
Figure 2 shows an example generating an output
frequency 3⅔ times the input frequency. Since the
output frequency is between 3 and 4 times the input, P is
set to 4. We need to select the P divider twice, and
select the P-1 divider once. Multiplying by 4 two times
out of three, and multiplying by 3 one time out of three,
averages to a multiplication of 3⅔.
The top waveform is the reference input. The bottom
waveform is the multiplied output. The waveform in the
middle shows those edges from the output that most
closely matches a corresponding reference waveform
edge.
The control circuit must generate a repeating pattern to
the mux of something like “101,” so that the P divider is
selected twice, and the P-1 divider is selected once,
every three reference edges.
Fractional-N Phase-Frequency Detector
This circuit, besides generating “pump up” and “pump
down” signals, also generates delta phase signals for
use by the lock detect circuit.
This detector circuit also accepts a gating signal from the
Fractional-N control block. When gated, the phase
detector generates neither pump up nor pump down
pulses.
Fractional-N Charge Pump
This circuit converts the “pump up” and “pump down”
signals from the phase-frequency detector into current
pulses. An external loop filter integrates these current
pulses into a control voltage.
Charge pump current is selectable. This modifies loop
gain as follows:
During acquisition of the reference, the charge
pump current is fixed at 20µA. Once the
acquisition sequencer has completed center
frequency trimming, then it changes the current
of this charge pump to 50µA.
Fractional-N VCO
This circuit converts the voltage integrated by the
external loop filter into a digital clock stream. The
frequency of this clock varies based on this control
voltage. This VCO has a coarse and a fine input, with a
combined range of 540MHz to 729MHz. The coarse
input trims the VCO, as described below, so that its
center frequency rests near the target frequency to
generate. The fine adjustment forms part of the closed
loop. VCO gain is nominally 200MHz per volt.
Fractional-N P/P-1 Divider
This is the main divider for the fractional-N loop. The
logical value of the output of the control block (Figure 1)
defines whether the divider divides by P (values shown
in Table 1) or by P-1. The expression for the fractional
division becomes:
Fractional Division = P ±
( )
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡
+
±
±
P
Q
1P
Q
1P
Q
Where QP is the number or reference clock periods
during which the divider must divide by P and QP–1 is the
number of reference clock periods during which the
divider must divide by P-1.
or (408) 955-1690
Produktspecifikationer
| Varumärke: | Microchip |
| Kategori: | Inte kategoriserad |
| Modell: | SY87729L |
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