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1

Data sheet acquired from Harris Semiconductor

SCHS195C

Features

•Simultaneous and Independent Read and Write

Operations

•Expandable to 512 Words of n-Bits

•Three-State Outputs

•Organized as 4 Words x 4 Bits Wide

•Buered Inputs

•Typical Read Time = 16ns for ’HC670 V

CC = 5V, CL=

15pF, TA = 25oC

•Fanout (Over Temperature Range)

-Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads

-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

•Wide Operating Temperature Range . . .-55oC to 125oC

•Balanced Propagation Delay and Transition Times

•Significant Power Reduction Compared to LSTTL

Logic ICs

•HC Types

-2V to 6V Operation

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il≤µ1A at V

OL, VOH

Description

The ’HC670 and CD74HCT670 are 16-bit registerfiles

organized as 4 wordsx4 bits each. Read and write address

and enable inputsallow simultaneouswriting into one location

while readinganother. Four datainputs are provided tostore

the 4-bit word. The write address inputs (WA0 and WA1)

determine the locationof thestored word inthe register.

When write enable (WE) is low the word is entered into the

address locationand it remains transparentto the data. The

outputs willreflect thetrue form of the inputdata. When(WE)

is high data and addressinputs are inhibited. Data acquisition

from the four registersismadepossible by thereadaddress

inputs (RA1 andRA0). The addressed word appears at the

output when the read enable(RE) is low. The output isin the

high impedance statewhen the (RE) is high. Outputs can be

tied together to increase the word capacity to 512 x 4 bits.

Pinout

CD54HC670

(CERDIP)

CD74HC670, CD74HCT670

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(oC) PACKAGE

CD54HC670F3A-55 to 12516 Ld CERDIP

CD74HC670E-55 to 12516 Ld PDIP

CD74HC670M-55 to 12516 Ld SOIC

CD74HC670MT-55 to 12516 Ld SOIC

CD74HC670M96-55 to 12516 Ld SOIC

CD74HCT670E-55 to 12516 Ld PDIP

CD74HCT670M-55 to 12516 Ld SOIC

CD74HCT670MT-55 to 12516 Ld SOIC

CD74HCT670M96-55 to 12516 Ld SOIC

NOTE:When ordering, use the entire part number. The suffix 96

denotes tape and reel. The suffix T denotes a small-quantity reel of

250.

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

D1

D2

D3

RA1

RA0

Q3

GND

Q2

VCC

WA0

WA1

WE

RE

Q0

Q1

D0

January 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright © 2003, Texas Instruments Incorporated

CD54HC670, CD74HC670,

CD74HCT670

High-Speed CMOS Logic

4x4 Register File

[ /Title

(CD74H

C670,

CD74H

CT670)

/Subject

(High-

Speed

CMOS

Logic

4x4 Reg-

ister

Produktspecifikationer