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SN74AHC125D
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1OE
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1A 1Y
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2OE
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2A 2Y
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3OE
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3A 3Y
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4OE
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4A 4Y
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHC125
,
SN74AHC125
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
SNx4AHC125 Quadruple Bus Buer Gates With 3-State Outputs
1
1 Features
1
• Operating Range: 2 V to 5.5 V
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Four Individual Output Enable Pins
• All Inputs Have Schmitt-Trigger Action
2 Applications
• Flow Meters
• Programmable Logic Controllers
• Power Over Ethernet (PoE)
• Motor Drives and Controls
• Electronic Point-of-Sale
3 Description
The SNx4AHC125 devices are quadruple bus buer
gates featuring independent line drivers with 3-state
outputs. Each output is disabled when the associated
output-enable (OE) input is high. When OE is low, the
respective gate passes the data from the A input to
its Y output.
To ensure the high-impedance state during power up
or power down, OE must be tied to V CC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Device Information(1)
PART NUMBER PACKAGE (PINS) BODY SIZE (NOM)
SNx4AHC125FK LCCC (20) 8.89 mm 8.89 mm
SNx4AHC125DB SSOP (14) 6.20 mm 5.30 mm
SNx4AHC125D SOIC (14) 8.65 mm × 3.91 mm
SNx4AHC125NS SO (14) 10.30 mm × 5.30 mm
SNx4AHC125W CFP (14) 9.21 mm × 5.97 mm
SNx4AHC125DGV TVSOP (14) 3.60 mm × 4.40 mm
SNx4AHC125PW TSSOP (14) 5.00 mm × 4.40 mm
SNx4AHC125N PDIP (14) 19.30 mm × 6.35 mm
SNx4AHC125RGY VQFN (14) 3.50 mm × 3.50 mm
SNx4AHC125J CDIP (14) 19.56 mm × 6.67 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
Produktspecifikationer
| Varumärke: | Texas Instruments |
| Kategori: | Inte kategoriserad |
| Modell: | SN74AHC125D |
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