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© 2009 Microchip Technology Inc. DS39705B-page 17-1
10-Bit A/D
Converter
17
Section 17. 10-Bit A/D Converter
HIGHLIGHTS
This section of the manual contains the following major topics:
17.1 Introduction ................................................................................................................. 17-2
17.2 A/D Terminology and Conversion Sequence .............................................................. 17-4
17.3 Registers..................................................................................................................... 17-6
17.4 A/D Module Configuration ......................................................................................... 17-13
17.5 Initialization ............................................................................................................... 17-16
17.6 Controlling the Sampling Process ............................................................................. 17-17
17.7 Controlling the Conversion Process.......................................................................... 17-17
17.8 A/D Results Buffer..................................................................................................... 17-23
17.9 Conversion Sequence Examples.............................................................................. 17-25
17.10 A/D Sampling Requirements..................................................................................... 17-33
17.11 Transfer Function ...................................................................................................... 17-34
17.12 A/D Accuracy/Error ................................................................................................... 17-35
17.13 Operation During Sleep and Idle Modes................................................................... 17-35
17.14 Effects of a Reset...................................................................................................... 17-36
17.15 Register Maps........................................................................................................... 17-37
17.16 Electrical Specifications............................................................................................. 17-38
17.17 Design Tips ............................................................................................................... 17-39
17.18 Related Application Notes......................................................................................... 17-40
17.19 Revision History ........................................................................................................ 17-41
PIC24F Family Reference Manual
DS39705B-page 17-2 © 2009 Microchip Technology Inc.
17.1 INTRODUCTION
The PIC24F 10-bit A/D Converter has the following key features:
Successive Approximation Register (SAR) Conversion
Conversion Speeds of up to 500 ksps
Up to 16 External Analog Input Channels
Multiple Internal Reference Input Channels (select devices only)
External Voltage Reference Input Pins
Unipolar Differential Sample-and-Hold (S/H) Amplifier
Automatic Channel Scan mode
Selectable Conversion Trigger Source
16-Word Conversion Result Buffer
Selectable Buffer Fill modes
Four Options for Results Alignment
Operation during CPU Sleep and Idle modes
The 10-bit A/D Converter module accepts a single analog signal at any one instant and converts
it to a corresponding 10-bit digital value. It accomodates up to 16 analog inputs and separate ref-
erence inputs; the actual number available on a particular device depends on the package size.
The heart of the module is a Successive Approximation Register (SAR) type of A/D Converter.
Hardware features surrounding the SAR provide flexible configuration and hardware support for
automatic operation, and minimize software overhead, especially in high-speed operation. The
three major sections surrounding the ADC are analog input selection, a memory mapped output
buffer, and timing and control functions.
An internal Sample-and-Hold (S/H) amplifier acquires a sample of an input signal, then holds that
value constant during the conversion process. A combination of input multiplexers selects the
signal to be converted from multiple analog input pins. The whole multiplexer path includes pro-
vision for differential analog input, although the number of negative input pins is limited, and the
signal difference must remain positive (i.e., unipolar). The sampled voltage is held and converted
to a digital value, which strictly speaking, represents the ratio of that input voltage to a reference
voltage. Configuration choices allow connection of an external reference or use of the device
power and ground (AVDD and AVSS). Reference and input signal pins are assigned differently
depending on the particular device.
An array of timing and control selections allow the user to create flexible scanning sequences.
Conversions can be started individually by program control, continuously free running, or triggered
by selected hardware events. A single channel may be repeatedly converted; alternate conver-
sions may be performed on two channels, or any or all of the channels may be sequentially
scanned and converted according to a user-defined bit map. The resulting conversion output is a
10-bit digital number which can be signed or unsigned, left or right justified.
Conversions are automatically stored in a dedicated 16-word buffer, allowing for multiple succes-
sive readings to be taken before software service is needed. Successive conversions are placed
into sequential buffer locations. Alternatively, the buffer can be split into two 8-word sections for
simultaneous conversion and read operations. The module sets its interrupt flag after a selectable
number of conversions, from one to sixteen, when the whole buffer can be read. After the interrupt,
the sequence restarts at the beginning of the buffer. When the interrupt flag is set according to the
earlier selection, scan selections and the Output Buffer Pointer return to their starting positions.
A simplified block diagram for the module is shown in Figure 17-1.
© 2009 Microchip Technology Inc. DS39705B-page 17-3
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
Figure 17-1: 10-Bit A/D Converter Block Diagram
Comparator
10-Bit SAR Conversion Logic
V +REF
DAC
AN12
AN13
AN14
AN15
AN8
AN9
AN10
AN11
AN4
AN5
AN6
AN7
AN0
AN1
AN2
AN3
V -REF
Sample Control
S/H
AVSS
AVDD
ADC1BUF0:
ADC1BUFF
AD1CON1
AD1CON2
AD1CON3
AD1CHS
AD1PCFG(L)
AD1PCFGH (2)
Control Logic
Data Formatting
Input MUX Control
Conversion Control
Pin Config. Control
Internal Data Bus
16
V +V - RR
MUX AMUX B
VINH
VINL
VINH
VINH
VINL
VINL
VR+
VR-
VR Select
VBG(1)
VBG/2(1)
AD1CSSL
AD1CSSH(2)
Note 1: Internal analog channels are implemented in select devices only. Different device families implement different
combinations of channels. Refer to the specific device data sheet for details.
2: Implemented in select devices only.
CTMU(1)
VDDCORE(1)
AVSS(1)
AVDD(1)
PIC24F Family Reference Manual
DS39705B-page 17-4 © 2009 Microchip Technology Inc.
17.2 A/D TERMINOLOGY AND CONVERSION SEQUENCE
Sample time is the time that the A/D module’s S/H amplifier is connected to the analog input pin.
The sample time may be started and ended automatically by the A/D Converter’s hardware or
under direct program control. There is a minimum sample time to ensure that the S/H amplifier
will give sufficient accuracy for the A/D conversion.
Conversion time is the time required for the A/D Converter to convert the voltage held by the
S/H amplifier. The conversion trigger ends the sampling time and begins an A/D conversion or a
repeating sequence. The conversion trigger sources can be taken from a variety of hardware
sources or can be controlled directly in software. An A/D conversion requires one A/D clock cycle
(TAD) to convert each bit of the result, plus two additional clock cycles, or a total of 12 TAD cycles
for a 10-bit conversion. When the conversion is complete, the result is loaded into one of 16 A/D
result buffers. The S/H can be reconnected to the input pin and a CPU interrupt may be gener-
ated. The sum of the sample time and the A/D conversion time provides the total A/D sequence
time. Figure 17-2 shows the basic conversion sequence and the relationship between intervals.
The conversion trigger sources can be taken from a variety of hardware sources, or can be
controlled directly by software. One of the conversion trigger options is an auto-conversion,
which uses a counter and the A/D clock to set the time between auto-conversions. The
Auto-Sample mode and auto-conversion trigger can be used together to provide continuous
automatic conversions without software intervention.
Figure 17-2: A/D Sample/Convert Sequence
Sample Time A/D Conversion Time
Total A/D Sequence Time
S/H amplifier is connected to
the analog input pin for sampling.
Input disconnected; S/H amplifier holds signal.
Conversion trigger starts A/D conversion.
Conversion complete, result is loaded
into A/D Buffer register.
Interrupt is generated (optional).
© 2009 Microchip Technology Inc. DS39705B-page 17-9
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
Register 17-3: AD1CON3: A/D Control Register 3
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: A/D Conversion Clock Source bit
1 = A/D internal RC clock
0 = Clock derived from system clock
bit 14-13 Unimplemented: Read as ‘0
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
11111 = 31 TAD
·····
00001 = 1 TAD
00000 = 0 TAD (not recommended)
bit 7-0 ADCS<7:0>: A/D Conversion Clock Period Select bits(1)
11111111
······ = Reserved
01000000
00111111 = 64 • Tcy
······
00000001 = 2 • TCY
00000000 = TCY
Note 1: Only valid when using the system clock as the conversion clock (ADRC = 0).
PIC24F Family Reference Manual
DS39705B-page 17-10 © 2009 Microchip Technology Inc.
Register 17-4: AD1CHS: A/D Input Channel Select Register
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB CH0SB4 (1) CH0SB3 CH0SB2 CH0SB1 CH0SB0
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA CH0SA4 (1) CH0SA3 CH0SA2 CH0SA1 CH0SA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: S/H Amplifier Negative Input Select for MUX B Multiplexer Setting bit
1 = Negative input is AN1
0 = Negative input is V R-
bit 14-13 Unimplemented: Read as ‘0
bit 12-8 CH0SB<4:0>: S/H Amplifier Positive Input Select for MUX B Multiplexer Setting bits (1)
The number of implemented analog inputs and the bit combinations assigned to them vary significantly
between device families. In general, external analog inputs, AN0 through AN15 (where implemented),
are sequentially assigned from 00000 as shown below. If a sequential input is unimplemented, its
corresponding bit value is also unimplemented.
In addition, some devices implement inputs for internal band gap references, external voltage
references, and other analog modules, such as the CTMU. Refer to the specific device data sheet for
a complete listing of implemented inputs for a particular device.
Any bit combinations not explicitly listed are unimplemented. Using an unimplemented channel for a
conversion will produce unpredictable results.
01111 = Positive input is AN15
01110 = Positive input is AN14
01101 = Positive input is AN13
01100 = Positive input is AN12
01011 = Positive input is AN11
01010 = Positive input is AN10
01001 = Positive input is AN9
01000 = Positive input is AN8
00111 = Positive input is AN7
00110 = Positive input is AN6
00101 = Positive input is AN5
00100 = Positive input is AN4
00011 = Positive input is AN3
00010 = Positive input is AN2
00001 = Positive input is AN1
00000 = Positive input is AN0
bit 7 CH0NA: S/H Amplifier Negative Input Select for MUX A Multiplexer Setting bit
1 = Negative input is AN1
0 = Negative input is V R-
bit 6-5 Unimplemented: Read as ‘0
bit 4-0 CH0SA<4:0>: S/H Amplifier Positive Input Select for MUX A Multiplexer Setting bits (1)
Implemented combinations are identical to those for CH0SB<4:0>.
Note 1: CH0SB4 and CH0SA4 are implemented in select devices only. Their implementation generally indicates
an extended range of input sources from voltage references and other analog modules.
© 2009 Microchip Technology Inc. DS39705B-page 17-13
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
17.4 A/D MODULE CONFIGURATION
All of the registers described in the previous section must be configured for module operation to
be fully defined. An effective approach is first to describe the signals and sequences for the par-
ticular application. Typically, it is an iterative process to assign signals to port pins, to establish
timing methods and to organize a scanning scheme, as well as to integrate the whole process
with the software design.
The various configuration and control functions of the module are distributed throughout the
module’s six (or eight) control registers. Control functions can be broadly sorted into four groups:
input, timing, conversion and output. Table 17-1 shows the register location of control or status
bits by register.
Table 17-1: A/D Module Fuctions by Registers and Bits
The following steps should be followed for performing an A/D conversion.
1. Configure the A/D module:
Select voltage reference source to match expected range on analog inputs
Select the analog conversion clock to match desired data rate with processor clock
Determine how sampling will occur
Set the multiplexer input assignments
Select the desired sample/conversion sequence
Select the output data format
Select the number of readings per interrupt
2. Configure A/D interrupt (if required):
Clear AD1IF bit
Select A/D interrupt priority
3. Turn on A/D module.
The options for each configuration step are described in the subsequent sections.
17.4.1 Selecting the Voltage Reference Source
The voltage references for A/D conversions are selected using the VCFG<2:0> control bits
(AD1CON2<15:13>). The upper voltage reference (VR+) and the lower voltage reference (VR-)
may be the internal AVDD and AVSS voltage rails or the VREF+ and VREF- input pins.
The external voltage reference pins may be shared with the AN0 and AN1 inputs on low pin count
devices. The A/D Converter can still perform conversions on these pins when they are shared
with the VREF+ and VREF- input pins.
The voltages applied to the external reference pins must meet certain specifications. Refer to
Section 17.16 “Electrical Specifications” for further details.
A/D Function Register(s) Specific Bits
Input AD1CON2 VCFG<2:0>, CSCNA, ALTS
AD1CHS CH0NB, CH0SB<4:0>, CH0NA, CH0SA<4:0>
AD1PCFG(H/L) PCFG<17:16>(1), PCFG<15:0>
AD1CSS(H/L) CSSL<17:16>(1), CSSL<15:0>
Conversion AD1CON1 ADON, ADSIDL, SSRC<2:0>, ASAM, SAMP, DONE
AD1CON2 SMPI<3:0>
Timing AD1CON3 ADRC, SAMC<4:0>, ADCS<7:0>
Output AD1CON1 FORM<1:0>
AD1CON2 BUFS, BUFM
Note 1: Implemented in select devices only.
Note: Do not write to the SSRC, ASAM, BUFS SMPI, BUFM and ALTS bits, or the
AD1CON3 and AD1CSSL registers, while ADON = 1; otherwise, indeterminate
conversion data may result.

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Modell: SY89468U

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