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SN74LV166ADR
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SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 5.5-V VCC Operation
DMax tpd of 10.5 ns at 5 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
DIoff Supports Partial-Power-Down-Mode
Operation
DSynchronous Load
DDirect Overriding Clear
DParallel-to-Serial Conversion
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV166A . . . J OR W PACKAGE
SN74LV166A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SN54LV166A . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SER
A
B
C
D
CLK INH
CLK
GND
VCC
SH/LD
H
QH
G
F
E
CLR
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
H
QH
NC
G
F
B
C
NC
D
CLK INH
A
SER
NC
CLR
E
V
SH/LD
CLK
GND
NC
CC
description/ordering information
The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC D
Tube of 40 SN74LV166AD
LV166A
SOIC − D Reel of 2500 SN74LV166ADR LV166A
SOP − NS Reel of 2000 SN74LV166ANSR 74LV166A
40° °C to 85 C
SSOP − DB Reel of 2000 SN74LV166ADBR LV166A
−40° °C to 85 C Tube of 90 SN74LV166APW
TSSOP − PW Reel of 2000 SN74LV166APWR LV166A
TSSOP PW
Reel of 250 SN74LV166APWT
LV166A
TVSOP − DGV Reel of 2000 SN74LV166ADGVR LV166A
CDIP − J Tube of 25 SNJ54LV166AJ SNJ54LV166AJ
−55° °C to 125 C CFP − W Tube of 150 SNJ54LV166AW SNJ54LV166AW
LCCC − FK Tube of 55 SNJ54LV166AFK SNJ54LV166AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%& "!&'& (
&)!*$'!& "#**%& ' !) +#,-"'!& '%. *!#" "!&)!*$ !
+%")"'!& +%* % %*$ !) %/' &*#$%& '&'* 0'**'&1.
*!#"!& +*!"%&2 !% &! &%"%'*-1 &"-#% %&2 !) '--
+'*'$%%*.
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
The ’LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an
overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input.
When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each
clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs
on the next clock pulse. During parallel loading, serial data ow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
These devices are fully specied for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
INPUTS
INTERNAL
CLR SH/LD CLK INH CLK SER PARALLEL
A . . . H Q
AQB
QH
L X X X X X L L L
H X L L X X QA0 QB0 QH0
H L L ↑X a . . . h a b h
H H L ↑H X H Q
An QGn
H H L ↑L X L Q
An QGn
H X H X X Q↑A0 QB0 QH0
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
15
9
7
6
13
SH/LD
CLR
CLK
CLK INH
QH
2 3 4 5 10 11 12 14
SER
A B C D E F G H
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
typical clear, shift, load, inhibit, and shift sequence
Clear Load
Inhibit
H
H
H
H
H
H H H H H
LLL
L
L
L
CLK
CLK INH
SER
A
B
C
D
E
F
G
H
SH/LD
CLR
QH
Parallel
Inputs
Serial Shift Serial Shift
Produktspecifikationer
| Varumärke: | Texas Instruments |
| Kategori: | Inte kategoriserad |
| Modell: | SN74LV166ADR |
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