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DS92LX1621,DS92LX1622

www.ti.com

SNLS327I–MAY2010–REVISEDJANUARY2014

DS92LX1621/DS92LX162210-50MHzDC-BalancedChannelLinkIIISerializerand

DeserializerwithBi-DirectionalControlChannel

CheckforSamples:DS92LX1621,DS92LX1622

1

FEATURES

•SERPackage:32PinWQFN(5mmx5mm)

•DESPackage:40PinWQFN(6mmx6mm)

2

•ConfigurableDataThroughput

–12–bit(min)upto600Mbits/sec

APPLICATIONS

–16–bit(def)upto800Mbits/sec

•IndustrialDisplays,TouchScreens

–18–bit(max)upto900Mbits/sec

•MedicalImaging

•10MHzto50MHzInputClockSupport

•EmbeddedClockwithDCBalancedCodingto

DESCRIPTION

SupportAC-CoupledInterconnects

TheDS92LX1621/DS92LX1622chipsetoffersa

•CapabletoDriveupto10MetersShielded

ChannelLinkIIIinterfacewithahigh-speedforward

Twisted-Pair

channelandafull-duplexbackchannelfordata

transmissionoverasingledifferentialpair.The

•Bi-DirectionalControlInterfaceChannelwith

Serializer/Deserializerpairistargetedfordirect

I

2

CSupport

connectionsbetweenautomotivecamerasystems

•I

2

CInterfaceforDeviceConfiguration.Single-

andHostController/ElectronicControlUnit(ECU).

pinIDAddressing

Theprimarytransportsends16bitsofimagedata

•16–bitDataPayloadwithCRC(Cyclic

overasinglehigh-speedserialstreamtogetherwitha

lowlatencybi-directionalcontrolchanneltransport

RedundancyCheck)forCheckingData

thatsupportsI

2

C.Includedwiththe16-bitpayloadis

IntegritywithProgrammableData

aselectabledataintegrityoptionforCRC(Cyclic

TransmissionErrorDetectionandInterrupt

RedundancyCheck)orparitybittomonitor

Control

transmissionlinkerrors.UsingTI’sembeddedclock

•Upto6ProgrammableGPIO's

technologyallowstransparentfull-duplex

•AT-SPEEDBISTDiagnosisFeaturetoValidate

communicationoverasingledifferentialpair,carrying

asymmetricalbi-directionalcontrolinformationwithout

LinkIntegrity

thedependencyofvideoblankingintervals.This

•IndividualPower-DownControlsforBothSER

singleserialstreamsimplifiestransferringawidedata

andDES

busoverPCBtracesandcablebyeliminatingthe

•User-SelectableClockEdgeforParallelData

skewproblemsbetweenparalleldataandclock

onBothSERandDES

paths.Thissignificantlysavessystemcostby

narrowingdatapathsthatinturnreducePCBlayers,

•IntegratedTerminationResistors

cablewidth,andconnectorsizeandpins.

•1.8V-or3.3V-CompatibleParallelBusInterface

Inaddition,theDeserializerinputsprovide

•SinglePowerSupplyat1.8V

equalizationcontroltocompensateforlossfromthe

•IEC61000–4–2ESDCompliant

mediaoverlongerdistances.InternalDCbalanced

•NoReferenceClockRequiredonDeserializer

encoding/decodingisusedtosupportAC-Coupled

interconnects.

•ProgrammableReceiveEqualization

•LOCKOutputReportingPintoEnsureLink

Thesleepfunctionprovidesapower-savingsmode

Status

andaremotewakeupinterruptforsignalingofa

remotedevice.

•EMI/EMCMitigation

TheSerializerisofferedina32-pinWQFNpackage,

–DESProgrammableSpreadSpectrum

andDeserializerisofferedina40-pinWQFN

(SSCG)Outputs

package.

–DESReceiverStaggeredOutputs

•TemperatureRange−40°Cto+85°C

1

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TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

2Alltrademarksarethepropertyoftheirrespectiveowners.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.

Copyright©2010–2014,TexasInstrumentsIncorporated

ProductsconformtospecificationsperthetermsoftheTexas

Instrumentsstandardwarranty.Productionprocessingdoesnot

necessarilyincludetestingofallparameters.

Produktspecifikationer