Texas Instruments LMX1404-EP Bruksanvisning

Läs gratis den bruksanvisning för Texas Instruments LMX1404-EP (70 sidor) i kategorin ej kategoriserat. Guiden har ansetts hjälpsam av 2 personer och har ett genomsnittsbetyg på 4.5 stjärnor baserat på 8 recensioner. Har du en fråga om Texas Instruments LMX1404-EP eller vill du ställa frågor till andra användare av produkten? Ställ en fråga

LMX1404-EP Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider

1 Features

•VID #V62/24627

•Clock buffer for 300MHz to 15GHz frequency

•Ultra-Low Noise

–Noise floor of –159dBc/Hz at 6GHz output

–36-fs additive jitter (100Hz to f

CLK

) at 6GHz

output

–5fs additive jitter (100Hz - 100MHz)

•4 high-frequency clocks with corresponding

SYSREF outputs

–Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and

8

–Shared programmable multiplier x2, x3, and x4

•Support pin mode options to configure the device

without SPI

•LOGICLK output with corresponding SYSREF

output

–On separate divide bank

–1, 2, 4 pre-divider

–1 (bypass), 2, …, 1023 post divider

•8 programmable output power levels

•Synchronized SYSREF clock outputs

–508 delay step adjustments of less than 2.5ps

each at 12.8GHz

–Generator and repeater modes

–Windowing feature for SYSREFREQ pins to

optimize timing

•SYNC feature to all divides and multiple devices

•2.5V operating voltage

•–55ºC to 125ºC operating temperature

•High Reliability

–Controlled Baseline

–One Assembly/Test Site

–One Fabrication Site

–Extended Product Life Cycle

–Product Traceability

2 Applications

•Radar imaging payload

•Communications payloads

•Command and data handling

•Data converter clocking

•Clock distribution/multiplication/division

3 Description

The LMX1404-EP is an buffer, divider and multiplier

that features high frequency, ultra-low jitter, and

SYSREF outputs. This device combined with an ultra-

low noise reference clock source is an exemplary

design for clocking data converters, especially when

sampling above 3GHz. Each of the 4 high frequency

clock outputs and additional LOGICLK output is

paired with a SYSREF output clock signal. The

SYSREF signal for JESD interfaces can either be

internally generated or passed in as an input and

re-clocked to the device clocks. This device can

distribute the multichannel, low skew, ultra-low noise

local oscillator signals to multiple mixers by disabling

the SYSREF outputs.

Package Information

PART NUMBERPACKAGE

(1)

PACKAGE SIZE

(2)

LMX1404MPAPTE

P

PAP (HTQFP, 64)10.00mm × 10.00mm

(1)For all available packages, see Section 10.

(2)The package size (length × width) is a nominal value and

includes pins, where applicable.

CLKOUT0

SYSREFOUT0

CLKIN

SYSREFREQ

÷1,2,4

rb_CLKPOS

xM

CAL

÷2,3,..,8

÷1,2,3,...1023

VCC_CLKIN

GND (x11)

VBIAS01

VCC01 (x2)

VCC23 (x2)

VBIAS23

÷1,2,4÷2,3,..4095

Pulser

÷2,4,8,16

Phase

Interpolator

CLKOUT1

SYSREFOUT1

CLKOUT2

SYSREFOUT2

CLKOUT3

SYSREFOUT3

LOGICLKOUT

LOGISYSREFOUT

Repeater

SYSREF

Windowing

and Capture

RESET

RESET

RESET

RESET

RESET

Con



nuous

SYSREF Genera



on & Distribu



on



0

Phase

Interpolator



1

Phase

Interpolator



2

Phase

Interpolator



3

Phase

Interpolator



4

IQ Phase Interpolator

Divider

Logic Clock & Logic SYSREF

RESETRESET

Digital

Control

PWRSEL2

PWRSEL1

PWRSEL0

DIVSEL2

DIVSEL1

DIVSEL0

MUXSEL1

MUXSEL0

SYSREF_EN

LOGIC_EN

CLK3_EN

CLK2_EN

CLK1_EN

CLK0_EN

CE

CAL

MUXOUT

CS#

SDI

SCK

VCC_LOGICLK

Block Diagram

LMX1404-EP

SNAS882A – JUNE 2024 – REVISED JUNE 2025

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Produktspecifikationer